<p>Electrical Engineering Department</p><p>M.S. Final Oral Defense Optical Stressing and Formation of Stacking Faults in 4H-Silcon Carbide</p><p> by ANAND SUBRAMANIAM July 20, 2009 12:30 pm ERC 490</p><p>Committee: Dr. BRIAN SKROMME (chair) Dr. DIETER SCHRODER Dr. DRAGICA VASILESKA</p><p>Abstract</p><p>Silicon carbide (SiC) is an ideal semiconductor for use in power devices due to its high reverse breakdown voltage. Stacking faults (SFs) in SiC material act as quantum wells which trap electrons and act as recombination centers, thus reducing excess carrier density and degrading the forward voltage characteristics. A new photoluminescence</p><p>(PL) technique, termed “Scanning laser induced optical stress (SLIOS),” for generating and characterizing SFs in 4H-SiC has been developed and implemented. This technique uses a high power laser to generate SFs by carrier injection and then images them using suitable filters with the wavelength range of interest. Since SLIOS is a non-contact technique, it can be used on bare wafers without any processing. The set-up was calibrated to find optimum stress power and exposure times to be used and compared with electroluminescence. The technique was applied to a variety of wafers, including both Schottky and p-i-n structures. The growth and propagation of different types of stacking faults and their bounding dislocations were mapped with the system. The results are in accordance with established theories and compare well with the previous</p><p> observations of other groups. Different shapes and structures of stacking faults were observed, among them a possibly new structure with bar-like shape which luminesces at around 415 nm. The SLIOS technique has been adapted to map large areas of a wafer by stitching together smaller imaged areas to get a composite image. The SF coverage and its progression rate in different wafers were quantified. The important factors affecting</p><p>SF coverage were identified. Annealing experiments were conducted in conjunction with</p><p>PL to observe the shrinkage SFs. Full wafer mapping was also implemented to demonstrate the speed and efficiency of the technique.</p>