<p> M. Tech. II (Second) Semester Examination 2014-15</p><p>Course Code: MEC201 Paper ID: 0972408</p><p>Digital Systems Testing and Simulation with VHDL</p><p>Time: 3 Hours Max. Marks: 70 </p><p>Max Marks: 75</p><p>Note: Attempt six questions in all. Q. No. 1 is compulsory.</p><p>1. Answer any five of the following (limit your answer in 50 words). (4x5=20) a) What is difference between Logic and Fault Modeling? b) Explain Abstraction Levels. c) Discuss Asynchronous Machines in Brief. d) What do you understand Path Sensitization Method? e) Explain Effect of fan-out on circuits. f) What do you understand Concurrent Fault Simulation? g) What is difference Logic and Fault Simulation? h) What do you understand Test Pattern Generation?</p><p>2. What do you understand Testing. Explain difference between Test Evaluation and Test Generation with suitable diagram. (10)</p><p>3. Define Representation models of digital systems with across abstraction levels diagram. (10)</p><p>4. What do you understand Test Pattern? What is difference between Fault Equivalence and dominance? (10) 5. Define Algebraic Approaches and Structural Approaches. Explain in details checkpoint faults structural. (10)</p><p>6. What do you understand Logic and Fault simulation. Explain in details Delay Models for circuit simulation. (10)</p><p>7. Explain Fault Simulation. What is difference between Serial and Parallel Fault Simulation? (10)</p><p>8. Write short notes on any two of the following: (5+5) a) Critical Path Tracing b) Literal Position c) SSF Model d) Statistical Fault Analysis</p>