<p>N I K H E F N A T I O N A L I N S T I T U T E F O R N U C L E A R A N D H I G H E N E R G Y P H Y S I C S</p><p>Control-Box for the Outer Tracker Detector </p><p>Februari 2007 Project no.: 39200</p><p>Albert Zwart</p><p>Email: [email protected]</p><p>Version 2 </p><p>Abstract:</p><p>The Control Box supplies the Timing and Control signals and monitors the supply voltages and temperature of the Outer Tracker Frontend Boxes.</p><p>N I K H E F , D E P A R T M E N T O F P . O . b o x 4 1 8 8 2 , N L 1 0 0 9 D B A M S T E R D A M E L E C T R O N I C T E C H N O L O G Y Control Box 01-02-2007</p><p>Table of contents Table of contents...... 2 1. Introduction...... 3 2. Functional Description...... 4 2.1 Timing and Fast Control...... 5 2.2 Slow control and monitoring...... 5 3. FPGA...... 7 3.1 I2C register access...... 7 4. Front Connections...... 10 5. Assembly...... 12 6. Appendix...... 14 7. References...... 17</p><p>Modifications:</p><p>In BOM list : R1, R8, R10, R17 was 5.6 Ω, must be 0 Ω R19, R22, R24, R26, R27 was 560 Ω, must be 0 Ω Extra components to place: Elco of 33uF between + 6 V and Gnd Resistor of 2K9 on VinMonCB to Gnd, close to resistor R21 Resistor of 2K9 on -VinMonCB to Gnd, close to resistor R20 Resistor of 330 Ω between JRQ3, pin 25 and pin 26 Instead of R80, a resistor of 10 Ω (1208) to Gnd</p><p>2 Control Box 01-02-2007</p><p>1. Introduction The Outer Tracker stations consist of four planes of straw tubes. The planes are mounted two by two on frames that can be opened in two halves like curtains. Each Detector Curtain carries nine Front End Modules on both sides of the curtain with a Front End Box [1] at the top and bottom of the Front End Module. Control Boxes are used to control and monitor the Front End Boxes. Two Control boxes are mounted on a Detector curtain, one at the top of the curtain and one at the bottom, each controlling 18 Front-End Boxes. The connection to the Front-End Boxes is done with SCSI-2 type 50 pins high-density connectors and cables.</p><p>TFC Monitor Detector curtain Ground plane I2C</p><p>Slack-space for FE cables</p><p>Control Box</p><p>Overlap Control Box</p><p>LV Distribution Box</p><p>Control Box Cavern Counting Room Fiber Break-out Box Control Box HV Junction Box</p><p>HV Patchpanel LV supplies</p><p>Off-Detector Patch Panels</p><p>TFC,SPECS, Data fibers</p><p>Figure 1: Outer Tracker Half Station with mounted Distribution boxes</p><p>3 Control Box 01-02-2007</p><p>2. Functional Description</p><p>For the Timing and Fast Control the Control box houses a TTCrq mezzanine. The TFC signals are decoded and multiplexed to the Front-End Boxes. The slow control is realized with SPECS mezzanine it supplies the I2C busses to control the FE Boxes and the FPGA in the Control Box and it contains a DAC to monitor the voltages and temperature of the FE Boxes. The power requirements of the Control Box are +6V @ 2A and -6V @0.1A. In the connection from the power supply to the ground of the Control Box low-Ohmic resistors are placed to eliminate ground loop currents.</p><p>TTCrq Mezzanine FPGA 18x 40MHz BX Clock phase BXclock 18 QPLL 80 MHz shifters to FE0 - FE17</p><p>I2C 18x TFC TTCrx fiber BCreset ECreset L0reset Resets and Trigger broadcast to FE0 - FE17 decoder L0Accept</p><p>Test-pulse Test-pulse input 4 9x SPECS mezzanine 2 I2C-bus13 I C bus to FE9 - FE17 select 1 SPECS I2C interface ECS 9x select 0 2 I C bus reset to FE0 - FE8</p><p>18x</p><p>4 Test-pulses to FE0 - FE17 bit(25:8) 18 enable testpulse (0-17) Ext. Register</p><p>18x PuReset to FE0 - FE17 bit(7,28) power control bit(6:0)</p><p> analog input (5 - 0) ADC Analog Switches Monitor signals from FE0 - FE17</p><p>4 Control Box 01-02-2007</p><p>Figure 2: Block Diagram </p><p>2.1 Timing and Fast Control The BX-Clock is derived from the Clock40 signal from the QPLL [3] on the TTCrq mezzanine. It is fed to 18 Phase-Shifters in the FPGA that are controlled by I2C. The Phase-Shifters can independently shift the BX-Clock for the FE Box in steps of 6.25 ns. The L0-Accept is taken from the TTCrx [2] and fed to the 18 LVDS drivers this signal is synchronized with ClockDes1 in the TTCrx. The BCreset, ECreset and L0reset are decoded in the FPGA from the TTCrx broadcast register and synchronized with ClockDes1. There are two sources of Test Pulses; the decoded TTCrx broadcast Test Pulse -this Test Pulse is synchronous with Clockdes2- and the asynchronous Test Pulse input at the front panel. Four types of Test Pulses can be generated: TPodd-high, TPodd-low, TPeven-high and TPeven-low. Controlled by the I2C, the source and type of the Test Pulse can be selected.</p><p>Figure 3: Relations between the TFC signals</p><p>2.2 Slow control and monitoring The SPECS-Slave Mezzanine [4, 5] supplies the following functions: I2C-bus0 to control FE0 to FE8 I2C-bus1 to control FE9 to FE17 I2C-bus13 for the TTCrx and the FPGA, 32 bit Control register to control the analog switches for the ADC (bit6:0), the Test Pulse enable (bit25:8) and the power control (bit7, 28) of the FE-Boxes. ADC (DCU2) [6] to monitor power and temperature of the FE-Boxes and Control Box. The I2C-address of the TTCrx (0x50) is set by jumpers on the TTCrq mezzanine, the I2C-address of the FPGA (0x54) is programmed inside the FPGA and the I2C-bus14 accesses the ADC on the SPECS mezzanine. The bit assignment of the 32 bit Control Register is given in Table 1.</p><p>Control Register (6:0) Analog Switches Control Register (7) GOL Off (of all FEB s) Control Register (16:8) Enable Test Pulse FEB08 – FEB00 Control Register (25:17) Enable Test Pulse FEB17 – FEB09</p><p>5 Control Box 01-02-2007</p><p>Control Register (28) 2V5 Inhibit (of all FEB s)</p><p>Table 1: SPECS Control Register</p><p>The analog switches at the inputs of the ADC are controlled by Control Register (6:0). In Table 2 is shown which FE-Box is switched to the inputs of the ADC. </p><p>Control Register (6:0) Signals to ADC inputs 0x78 – 0x7B FEB00 – FEB03 0x74 – 0x77 FEB04 – FEB07 0x6C – 0x6F FEB08 – FEB11 0x5C – 0x5F FEB12 – FEB15 0x3C, 0x3D FEB16, FEB17 0x3E, 0x3F Control Box</p><p>Table 2: Analog Switch Control</p><p>Table 3 specifies which monitor signal is connected to the 6 ADC input channels.</p><p>ADC Control Register(6:0) Control Register(6:0) Control Register(6:0) input (FEB00 – FEB17) (Control Box 0x3E) (Control Box 0x3F) AIn0 Temperature Temperature NC AIn1 +3V monitor (1/3Vin) +5V monitor (1/3Vin) +Vin monitor (8/30Vin) AIn2 -3V monitor (1/3Vin+2.2) -5V monitor (1/3Vin+2.2) -Vin monitor (8/30Vin+2.2) AIn3 +2.5V monitor (1/3Vin) +2V5 monitor (1/3Vin) +3V3 monitor (1/3Vin) AIn4 +0V monitor (1/3Vin) NC 5V TTCrq (1/3Vin) AIn5 GOL-Ready/QPLL-Lock QPLL-Error/QPLL-Lock NC Status: Status: Ready and Lock = 1.5V Error and Lock = 1.5V Ready and not Lock = 1V Error and not Lock = 1V not Ready and Lock = 0.5V no Error and Lock = 0.5V not Ready and not Lock = 0V no Error and not Lock = 0V</p><p>Table 3: ADC Inputs</p><p>6 Control Box 01-02-2007</p><p>3. FPGA The FPGA is an ACTEL ProASICplus [] type APA075TQ100 it fulfills the following functions (see Figure 4):  Clock phase shifters (u1, u8 and u7) The 80 MHz clock from the QPLL is fed to the on chip PLL to get 160 MHz and 80 MHz clocks. With these signals stable clocks are generated with controllable phase differences of 6.25 ns. This is done in two blocks of nine clocks that can be separately enabled.  TTC broadcast decoder (u0) Two TTC broadcast messages are decoded; L0-Reset (chan b(7:2) = “010001”) and Calibration pulse (chan b(7:2) = “000100”)according to the ‘Requirements’[7]. L0-Reset is strobed with Clock40des1.  Test pulse generator (u0 and u6) Clock40des2 is stabilized with the on chip PLL, together with the Calibration pulse and under control of I2C; four Test Pulses with a pulse width of 12.5 ns are obtained.  I2C interface to control these functions (u3) The I2C Interface is a standard I2C slave interface [8] with a transfer rate of 400Kbit/sec it can access the five registers to control the clock shifters, one command register and one status register. The address of the interface is fixed at 0x54 and is programmed in the FPGA. All registers are 8bit wide, the register and bit assignments are given in Table 4  Miscellaneous logic like inverters for LED drivers (u4) All registers in the FPGA are build with the ‘triple voting’ mechanism to make it insensible to single event upsets (SEU). All SEU s are counted in a 6 bit counter in the status register bit(7:2), when all bits of the counter are ‘1’, the counter is in overflow. The counter can be reset by the command register (see Table 4).</p><p>3.1 I2C register access To write to one or more registers is accomplished by an I2C bus write cycle, in this cycle the bytes are generated by the master and the slave reacts with an acknowledge bit. The first byte of a write cycle contains the I2C address and the R/W_n bit (‘0’), the second byte contains the pointer to the register to write to, followed by the content of that register. The following bytes will be written in the subsequent registers. Writing to the status register will have no effect. The reading of the registers is done with an I2C bus read cycle, this cycle is initiated by the master with the I2C address and the R/W_n bit (‘1’), the slave reacts with an acknowledge bit followed by the contents of the register pointed to by the pointer register. The slave will continue sending the data of the consecutive registers until the master reacts with an acknowledge bit, and then the read cycle will be terminated. The pointer register must be written in a previous write cycle.</p><p>7 Control Box 01-02-2007</p><p>Figure 4: FPGA Schematics</p><p>8 Control Box 01-02-2007</p><p>Register Name Type Bit Description 0 Clock R/W 1,0 Clock 00 shift value register 3,2 Clock 01 shift value 5,4 Clock 02 shift value 7,6 Clock 03 shift value 1 Clock R/W 1,0 Clock 04 shift value register 3,2 Clock 05 shift value 5,4 Clock 06 shift value 7,6 Clock 07 shift value 2 Clock R/W 1,0 Clock 08 shift value register 3,2 Clock 09 shift value 5,4 Clock 10 shift value 7,6 Clock 11 shift value 3 Clock R/W 1,0 Clock 12 shift value register 3,2 Clock 13 shift value 5,4 Clock 14 shift value 7,6 Clock 15 shift value 4 Clock R/W 1,0 Clock 16 shift value register 3,2 Clock 17 shift value 5,4 not used 7,6 used intern must be ‘0’ 5 Command R/W 1,0 Test pulse select: register 00 = tpodd_low 01 = tpodd_hi 10 = tpeven_low 11 = tpeven_hi 2 select extern TP input 3 reset SEU counter 4 Disable clock FE00 - FE08 5 Disable clock FE09 -FE17 6 not used 7 Otis reset 6 Status R 0 PLL lock 80 MHz register 1 PLL lock 40 MHz 7-2 SEU counter</p><p>Table 4: Bit Assignment of I2C Registers</p><p>9 Control Box 01-02-2007</p><p>4. Front Connections The signal assignment of the 18 FE connectors is given in table 5, except for the monitor signals and GOL Ready and QPLL Lock all signals are LVDS type signals. The Monitor Return signals are connected to ground via a 1 KΩ resistor, so there is no direct connection between the ground of the FE boxes and the ground of the Control Box in the signal cable. This eliminates ground loop currents in the signal path.</p><p>Socket Signal Socket Signal 1 SDAms_p 26 SDAms_n 2 SDAsm_p 27 SDAsm_n 3 SCL_p 28 SCL_n 4 0V Monitor 29 0V Monitor Return 5 +3V Monitor 30 +3V Monitor Return 6 -3V Monitor 31 -3V Monitor Return 7 2V5 Monitor 32 2V5 Monitor Return 8 Temp. Monitor 33 Temp. Monitor Return 9 FigureGOL 5Ready: Scope outputs34 QPLL Lock 10 GOL Off_p 35 GOL Off_n 11 2V5 Inhibit_p 36 2V5 Inhibit_n For test and debugging 12 Spare 37 Spare purposes the TFC signals 13 TPOddLow_p 38 TPOddLow_n are available at Lemo type 14 TPOddHi_p 39 TPOddHi_n connectors with a LED 15 TPEvenLow_p 40 TPEvenLow_n below the connector(see 16 TPEvenHi_p 41 TPEvenHi_n figure 5). The LED flashes 17 Spare 42 Spare when the signal is active. 18 Spare 43 Spare The signal level of the 19 Spare 44 Spare 20 PUReset_n 45 PUReset_p 21 L0Reset_n 46 L0Reset_p 22 ECReset_n 47 ECReset_p 23 BCReset_n 48 BCReset_p 24 L0Acc_p 49 L0Acc_n scope outputs is an AC 25 BxClk_p 50 BxClk_n coupled negative going</p><p>Table 5: Signal Assignment of Front-End Connectors</p><p> pulse of about 190 mV into 50 Ω.</p><p>10 Control Box 01-02-2007</p><p>To enable random test pulse insertion there is a Test Pulse input available, this input is enabled when the LED is on (see table 4 –select extern TP input-). Figure 6 shows the scheme of the Test Pulse input it is an AC coupled pulse shaper that generates an output pulse on a negative going input signal of about 1 V</p><p>Figure 6: Test Pulse input</p><p>Figure 7 shows the front view of the power connector. In the gnd connection of The power consumption is 1 mA @ -6V and 2.7 A @ +6V.</p><p>Figure 7: Power Connector</p><p>5. Assembly Before applying power to the board it must be built together with the front panel that both acts as heat sink for the power regulators and as stiffener for the PCB. First the mounting of the TTCrq mezzanine must be realized as shown in Figure 8. On the TTCrq the I2C address must be set to 0x50, this is done by soldering a jumper to GND at ID 0, 1, 2 and 4 and a jumper to VCC at ID 3 and 5.</p><p>11 Control Box 01-02-2007</p><p>Figure 8</p><p>Then the PCB can be mounted on the front panel, this is shown in detail in Figure 9. It is important to use non conducting spacers on the PCB.</p><p>Figure 9</p><p>.</p><p>12 Control Box 01-02-2007</p><p>6. Appendix Freds representation of the Functions and Registers:</p><p>Each ControlBox contains only 1 SPECS-mezzanine, default SlaveID = 1</p><p>Each ControlBox uses several I2C-busses: Bus I2C-connection I2C-bus0 FE00-FE08 Upstream Layer (FE0-FE8) I2C-bus1 FE00-FE08 Downstream Layer (ex-FE9 - FE17) Bus 2 - 12 not used I2C-bus13 ClockDelay FE0u-FE8d, TestPulse & Status I2C-bus14 DCU-control I2C-bus15 not used</p><p>To control the Registers of IC's inside connected FEBoxes: Slave 1 Bus 0 (Upstream FEB's) 1 (Downstream FEB's) Address see below SubAddr 0</p><p>IC selection Destination Address mask SubAddr FE0 0001xxx 0xF8 FE1 0010xxx 0xF8 FE2 0011xxx 0xF8 FE3 0100xxx 0xF8 FE4 0101xxx 0xF8 FE5 0110xxx 0xF8 FE6 0111xxx 0xF8 FE7 1000xxx 0xF8 FE8 1001xxx 0xF8</p><p>GOL pointer xxxx100 0x07 GOL data xxxx101 0x07 OTIS0 xxxx000 0x07 OTIS1 xxxx001 0x07 OTIS2 xxxx010 0x07 OTIS3 xxxx011 0x07</p><p>13 Control Box 01-02-2007</p><p>To Control the TrigDelays, TestPulses and Status Slave 1 Bus 13 Address see below SubAddr 0</p><p>Clock-Delay's TestPulse ClockDelay Address Mask Function Address Mask Data FE0-up 0x00 0x03 TPodd_lo 0x05 0x03 0x00 FE1-up 0x00 0x0C TPodd_hi 0x05 0x03 0x01 FE2-up 0x00 0x30 TPeven_lo 0x05 0x03 0x02 FE3-up 0x00 0xC0 TPeven_hi 0x05 0x03 0x03 FE4-up 0x01 0x03 Select external TPinput 0x05 0x04 0x04 FE5-up 0x01 0x0C Selection of TestPulse kind , FE6-up 0x01 0x30 TestPulse ONOFF via ControlRegister FE7-up 0x01 0xC0 FE8-up 0x02 0x03 Resets Function Address Mask Data FE0-down 0x02 0x0C Reset SEU counter 0x05 0x08 0x08 FE1-down 0x02 0x30 OTIS Reset 0x05 0x80 0x80 FE2-down 0x02 0xC0 FE3-down 0x03 0x03 Clock FE4-down 0x03 0x0C Function Address Mask Data FE5-down 0x03 0x30 Disable clock FE0-FE8-up 0x05 0x10 0x10 FE6-down 0x03 0xC0 Disable clock FE0-FE8-dwn 0x05 0x20 0x20 FE7-down 0x04 0x03 FE8-down 0x04 0x0C Status Function Address Mask Data PLL lock 80MHz 0x06 0x01 PLL lock 160MHz 0x06 0x02 SEU counter 0x06 0xFC</p><p>Each ControlBox has a 32bit 'Control-Register' (also called 'External Register' or 'RegOut' register) Slave 1 Register see below</p><p>( 0x2 MSW CtrlRegister-Output enable 0x3 LSW CtrlRegister-Output enable ) ( 0x0 MSW CtrlRegister-Data 0x1 LSW CtrlRegister-Data )</p><p>ControlRegister Output Enable: I2C-Register 0x2 & 0x3 15 I2C - Register 2 0 15 I2C - Register 3 0 ConfRegOutMSB ConfRegOutLSB</p><p>ControlRegister Data: I2C-Register 0x0 & 0x1 15 I2C - Register 0 0 15 I2C - Register 1 0 RegOutMSB RegOutLSB MSB LSB 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 | FE8 FE0 FE8 FE0 | | Enable TestPulse Enable TestPulse | DCU multiplexer | FExx Downstream Layer FExx Upstream Layer | 2.5V inhibit GOL-OnOff 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0</p><p>14 Highlevel 'fwDCU' functions: FE-Box DCU-Multiplexer - fwSpecs_DCUReset 6 5 4 3 2 1 0 - fwSpecs_DCUInitialise FE0 upstream FE00 0x78 1 1 1 1 0 0 0 - fwSpecs_DCUSetMode FE1 upstream FE01 0x79 1 1 1 1 0 0 1 - fwSpecs_DCUReadMode FE2 upstream FE02 0x7A 1 1 1 1 0 1 0 - fwSpecs_DCUAcquire FE3 upstream FE03 0x7B 1 1 1 1 0 1 1 - fwSpecs_DCURegisterWrite FE4 upstream FE04 0x74 1 1 1 0 1 0 0 - fwSpecs_DCURegisterWriteRead FE5 upstream FE05 0x75 1 1 1 0 1 0 1 - fwSpecs_DCURegisterRead FE6 upstream FE06 0x76 1 1 1 0 1 1 0 FE7 upstream FE07 0x77 1 1 1 0 1 1 1 FE8 upstream FE08 0x6C 1 1 0 1 1 0 0 FE0 downstream FE09 0x6D 1 1 0 1 1 0 1 FE1 downstream FE10 0x6E 1 1 0 1 1 1 0 FE2 downstream FE11 0x6F 1 1 0 1 1 1 1 FE3 downstream FE12 0x5C 1 0 1 1 1 0 0 FE4 downstream FE13 0x5D 1 0 1 1 1 0 1 FE5 downstream FE14 0x5E 1 0 1 1 1 1 0 FE6 downstream FE15 0x5F 1 0 1 1 1 1 1 FE7 downstream FE16 0x3C 0 1 1 1 1 0 0 FE8 downstream FE17 0x3D 0 1 1 1 1 0 1 CtrlBox-gr0 0x3E 0 1 1 1 1 1 0 CtrlBox-gr1 0x3F 0 1 1 1 1 1 1 Control Box 01-02-2007</p><p>15 Control Box 01-02-2007</p><p>7. References [1] U.Uwer, D.Wiedner “Auxiliary Board for the Outer Tracker” version 3.0 LHCb-2005-xxx</p><p>[2] J.Christiansen, A.Marchioro, P.Moreira, T.Toifl “TTCrx Reference Manual version 3.6” June 2002</p><p>[3] Paulo Moreira “QPLL User Manual” 2003-04-9</p><p>[4] Dominique Breton, Daniel Charlet “SPECS: the Serial Protocol for the Experiment Control System of LHCb” LHCb 2003-004 </p><p>[5] Dominique Breton, Daniel Charlet “The SPECS Slave mezzanine board” LHCb xxxx- xx June 2004 </p><p>[6] G. Magazzu, A. Marchioro, Paulo Moreira “DCUF User Guide” November 2003</p><p>[7] Jorgen Christiansen “TTCrx Requirements to the L0 front-end electronics” LHCb 2001-014</p><p>[8] Philips Semiconductor “The I2C-Bus Specification” version 2.1 January 2000</p><p>16</p>