<p>1. VHDL a. Write a VHDL architecture for a decoder 2/4. Note: if En=’0’ then none of the decoder outputs is asserted; if En=’1’ then input I determines which of the outputs is asserted. library ieee; use ieee.std_logic_1164.all; entity dec2to4 is port( En: in std_logic; I: in std_logic_vector(1 downto 0); O: out std_logic_vector(3 downto 0) ); end dec2to4;</p><p> b. Write a VHDL architecture for a 4-bit latch register with inverted gate (if Gn=‘0’ the output Q follows the changes on the input D) and asynchronous clear active in logic ‘1’. library ieee; use ieee.std_logic_1164.all; entity latch is port( D : in std_logic_vector(3 downto 0); Gn, Cl : in std_logic; Q : out std_logic_vector(3 downto 0)); end latch; c. Write a generic VHDL model (the size is specified during instantiation) that describes a counter following characteristics. Signal Cln (Clear) is asynchronous and active low. All other state changes occur on the falling edge of the Clock signal. If the control inputs S0=S1=1 the counter is loaded in parallel. If S0=0, S1 = 1, the counter counts up, if S0=1, S1=0 it counts down. If S0=S1=0, no action occurs. 2. VHDL Consider the following fragment of a VHDL code. type My4 is (‘a’, ‘b’, ‘c’, ‘d’); type My4_vector is array(natural range <>) of My4; function myresolve(s: My4_vector) return My4; subtype My4R is myresolve My4; ...</p><p> signal R : My4R := ‘d’; The resolution function myresolve realizes the signal resolution using the following table. ‘a’ ‘b’ ‘c’ ‘d’ ‘a’ ‘a’ ‘a’ ‘a’ ‘a’ ‘b’ ‘a’ ‘b’ ‘b’ ‘b’ ‘c’ ‘a’ ‘b’ ‘c’ ‘c’ ‘d’ ‘a’ ‘b’ ‘c’ ‘d’</p><p>Give values of the signal R in time interval from 0 ns to 20 ns assuming that it’s driven by the following concurrent signal assignment statements. R <= transport ‘a’ after 4 ns, ‘b’ after 3 ns; R <= transport ‘c’ after 2 ns, ‘d’ after 6 ns; R <= transport ‘d’ after 1 ns, ‘c’ after 5 ns; 3. SystemC Write a SystemC model for the following state machine.</p><p>1/Z3</p><p>S0/- S1/Z2</p><p>0/Z3 1/Z3 0/- 1/Z3 S2/Z1</p><p>0/-</p><p>4. VLSI Trends, Power Discuss the state-of-the-art and technology trends for the on-chip interconnect (wires). Notes: Discuss wire sizing and its influence on resistance and capacitance; Describe how does it influence power consumption; ... 5. Synthesis</p>