Open NAND Flash Interface Specification Revision 4.0 04 02 2014 Intel Corporation Micron Technology, Inc. Phison Electronics Corp. SanDisk Corporation SK Hynix, Inc. Sony Corporation Spansion This 4.0 revision of the Open NAND Flash Interface specification ("Final Specification") is available for download at www.onfi.org. SPECIFICATION DISCLAIMER THIS SPECIFICATION IS PROVIDED TO YOU “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, NON- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE. THE AUTHORS OF THIS SPECIFICATION DISCLAIM ALL LIABILITY, INCLUDING LIABILITY FOR INFRINGEMENT OF ANY PROPRIETARY RIGHTS, RELATING TO USE OR IMPLEMENTATION OF INFORMATION IN THIS SPECIFICATION. THE AUTHORS DO NOT WARRANT OR REPRESENT THAT SUCH USE WILL NOT INFRINGE SUCH RIGHTS. THE PROVISION OF THIS SPECIFICATION TO YOU DOES NOT PROVIDE YOU WITH ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS. Copyright 2005-2014, Intel Corporation, Micron Technology, Inc., Phison Electronics Corp., SanDisk Corporation, SK Hynix, Inc., Sony Corporation, Spansion. All rights reserved. For more information about ONFI, refer to the ONFI Workgroup website at www.onfi.org. All product names are trademarks, registered trademarks, or servicemarks of their respective owners. ONFI Workgroup Technical Editor: mailto: Terry Grunzke Micron Technology 8000 S. Federal Way Boise, ID 83707-0006 USA Tel: (208)-368-4960 Email: [email protected] ii Table of Contents 1. Introduction ............................................................................................................................... 1 1.1. Goals and Objectives ........................................................................................................ 1 1.2. EZ NAND Overview .......................................................................................................... 1 1.3. References ........................................................................................................................ 1 1.4. Definitions, abbreviations, and conventions ...................................................................... 1 1.4.1. Definitions and Abbreviations .................................................................................... 1 1.4.2. Conventions ............................................................................................................... 5 2. Physical Interface ..................................................................................................................... 8 2.1. TSOP-48 and WSOP-48 Pin Assignments ....................................................................... 8 2.2. LGA-52 Pad Assignments ............................................................................................... 11 2.3. BGA-63 Ball Assignments ............................................................................................... 13 2.4. BGA-100 Ball Assignments ............................................................................................. 17 2.5. BGA-152 and BGA-132 Ball Assignments ...................................................................... 20 2.6. BGA-272 and BGA-316 Ball Assignments ...................................................................... 23 2.7. Signal Descriptions ......................................................................................................... 29 2.8. CE_n Signal Requirements ............................................................................................. 45 2.8.1. Requirements for CLK (NV-DDR) ............................................................................ 45 2.9. Absolute Maximum DC Ratings ...................................................................................... 45 2.10. Recommended DC Operating Conditions ................................................................... 46 2.10.1. I/O Power (VccQ) and I/O Ground (VssQ) ........................................................... 47 2.11. AC Overshoot/Undershoot Requirements ................................................................... 47 2.12. DC and Operating Characteristics ............................................................................... 49 2.12.1. Single-Ended Requirements for Differential Signals ............................................ 57 2.12.2. VREFQ Tolerance ................................................................................................ 57 2.13. Calculating Pin Capacitance ....................................................................................... 59 2.14. Staggered Power-up .................................................................................................... 59 2.15. Power Cycle Requirements ......................................................................................... 59 2.16. Independent Data Buses ............................................................................................. 59 2.17. Bus Width Requirements ............................................................................................. 60 2.18. Ready/Busy (R/B_n) Requirements ............................................................................ 60 2.18.1. Power-On Requirements ...................................................................................... 60 2.18.2. R/B_n and SR[6] Relationship ............................................................................. 61 2.19. Write Protect ................................................................................................................ 61 2.20. CE_n Pin Reduction Mechanism ................................................................................. 62 2.20.1. Volume Appointment when CE_n Reduction Not Supported .............................. 65 3. Memory Organization ............................................................................................................. 67 3.1. Addressing ...................................................................................................................... 68 3.1.1. Multi-plane Addressing ............................................................................................ 69 3.1.2. Logical Unit Selection .............................................................................................. 70 3.1.3. Multiple LUN Operation Restrictions ........................................................................ 70 3.2. Volume Addressing ......................................................................................................... 71 3.2.1. Appointing Volume Address .................................................................................... 71 3.2.2. Selecting a Volume .................................................................................................. 71 3.2.3. Multiple Volume Operations Restrictions ................................................................. 71 3.2.4. Volume Reversion .................................................................................................... 72 3.3. Factory Defect Mapping .................................................................................................. 74 3.3.1. Device Requirements............................................................................................... 74 3.3.2. Host Requirements .................................................................................................. 74 3.4. Extended ECC Information Reporting ............................................................................. 75 3.4.1. Byte 0: Number of bits ECC correctability ............................................................... 75 3.4.2. Byte 1: Codeword size ............................................................................................. 76 3.4.3. Byte 2-3: Bad blocks maximum per LUN ................................................................. 76 3.4.4. Byte 4-5: Block endurance ....................................................................................... 76 3.5. Discovery and Initialization.............................................................................................. 76 iii 3.5.1. Discovery without CE_n pin reduction ..................................................................... 76 3.5.2. Discovery with CE_n pin reduction .......................................................................... 77 3.5.3. Target Initialization ................................................................................................... 80 4. Data Interface and Timing ...................................................................................................... 81 4.1. Data Interface Type Overview ........................................................................................ 81 4.2. Signal Function Assignment............................................................................................ 82 4.3. Bus State ......................................................................................................................... 82 4.3.1. SDR.......................................................................................................................... 83 4.3.2. NV-DDR ................................................................................................................... 83 4.3.3. NV-DDR2 and NV-DDR3 ......................................................................................... 84 4.3.4. Pausing Data Input/Output .....................................................................................