MODELING THE EFFECT OF VELOCITY SATURATION IN NANOSCALE MOSFET MICHAEL TAN LOONG PENG UNIVERSITI TEKNOLOGI MALAYSIA iii To my wonderful parents and family, for their guidance, support, love and enthusiasm. I am so thankful for that blessing and for the example you both are to me over the years. I would not have made it this far without your motivation and dedication to my success. Thank you, mom and dad, I love you both. iv ACKNOWLEDGEMENTS First of all, I am thankful to my supervisor, Associate Professor Dr Razali Ismail for his precious insight, guidance, advice and time. I would like to take this opportunity to record my sincere gratitude for his supports and dedication throughout the years. My thankfulness also goes to my manager in Intel Penang Design Center, Mr Ravisangar Muniandy. His immense support and encouragement was keeping me going during the times when I was encountering problems at every turn. I wish to express my most heartfelt thankre abroad and even made themselves available when I had questions after our meeting. I thank the many good friends I met here, Kaw Kiam Leong, Ng Choon Peng, Lee Zhi Feng and many others for the encouragement and unforgettable memories. They have always given me the chance to discuss my academic issues as well as my personal issues. Without them, I could not have been completed my study. Very valuable advice was also given by fellow friend, Dr Kelvin Kwa for his sharing of experience, sachets of tea and coffee, books and advices. Also, thank to my friends Sim Tze Yee, Liu Chin Foon, Liew Eng Yew, Gan Hock Lai and Alvin Goh Shing Cyhe. I cherish the ideas they have given me, their support and warmhearted friendship. On a personal note, I would like to thank my family who has always supported me and the encouragement they have given me. v ABSTRACT MOSFET scaling throughout the years has enabled us to pack million of MOS transistors on a single chip to keep in pace with Moore’s Law. The introduction of 65 nm and 90 nm process technology offer low power, high-density and high- speed generation of processor with latest technological advancement. When gate length is scaled into nanoscale regime, second order effects are becoming a dominant issue to be dealt with in transistor design. In short channel devices, velocity saturation has redefined the current-voltage (I-V) curve. New models have been modified and studied to provide a better representation of device performance by understanding the effect of quantum mechanical effect. This thesis studies the effect of velocity saturation on transistor’s internal characteristic and external factor. Velocity saturation dependence on temperature, substrate doping concentration and longitudinal electric field for n-MOSFET are investigated. An existing current- voltage (I-V) compact model is utilized and modified by appending a simplified threshold voltage derivation and a more precise carrier mobility model. The compact model also includes a semi empirical source drain series resistance modeling. The model can simulate the performance of the device under the influence of velocity saturation. The results obtained can be used as a guideline for future nanoscale MOS development. vi ABSTRAK Penskalaan mendadak MOSFET dari tahun ke tahun selari dengan Hukum Moore membolehkan berjuta-juta transistor dimuatkan ke dalam serpihan silikon. Berikutan pengenalan teknologi proses 65 nm and 90 nm, arus pembaharuan yang dramatik telah membawa kepada penumpuan pemproses yang pantas, berkuasa rendah dan berdensiti tinggi dengan pendekatan teknologi terbaru. Kesan tertib kedua menjadi satu isu dominan untuk ditangani dalam rekaan transistor apabila panjang saluran mencecah nanometer. Salah satu daripandanya ialah halaju tepu yang telah membawa definasi baru bagi ciri-ciri voltan and arus (I-V) dalam peranti saluran/kanal pendek. Model-model baru telah diperkenalkan untuk memberi representasi prestasi yang jelas dengan mengambil kira teori fizik kuantum. Penyelidikan ini bertujuan untuk meneliti kesan halaju tepu ke atas faktor luaran dan dalam ke atas transistor. Hubungan hanyut dan halaju tepu dengan suhu, kepekatan pendopan and medan elektrik diperhatikan. Model voltan-arus (I-V) sedia ada digabungkan bersama model kebolehgerakan elektron yang lebih terperinci untuk menganalisis parameter-parameter di atas. Model padat tersebut juga mengandungi model perintang bersiri sumber-salir semiempirik. Persamaan voltan ambang telah diterbitkan dan berupaya memberikan ketepatan yang sama dengan silikon sebenar dan dibuktikan dengan teknik kesesuaian pemadanan. Melalui pendekatan simulasi, model-model ini dapat memberi prestasi peranti di bawah pengaruh halaju tepu. Keputusan penyelidikan ini boleh digunakan sebagai panduan untuk perkembangan MOS pada masa depan. vii TABLE OF CONTENTS CHAPTER TITLE PAGE DECLARATION ii DEDICATION iii ACKNOWLEDGEMENTS iv ABSTRACT v ABSTRAK vi TABLE OF CONTENTS vii LIST OF TABLES xi LIST OF FIGURES xii LIST OF ABBREVIATIONS xvi LIST OF SYMBOLS xviii 1 INTRODUCTION 1 1.1 Background 1 1.2 Problem Statements 4 1.3 Objectives 5 1.4 Research Scope 5 1.5 Contributions 6 1.6 Thesis Organization 7 2 LITERATURE REVIEW 9 2.1 Non Ideal Effects in MOSFET 9 2.2 Velocity Saturation 10 viii 2.3 Oxide Charges and Traps 13 2.4 Device Modeling 15 2.5 SPICE Model 16 2.6 Threshold Voltage Model 17 2.7 Mobility Model 17 2.8 Drain Current and Voltage Model (I-V) 18 2.9 Velocity Field Model 19 2.10 Source/Drain Series Resistance Model 21 2.11 Hot Carrier Effects 22 2.12 Reducing Hot Carrier Degradation 24 3 RESEARCH METHODOLOGY 29 3.1 Velocity Saturation Electrical Modeling 29 3.2 Intel Proprietary Softwares 31 3.3 Parameters Extraction for Proposed 32 Model 3.4 MOSFET Modeling for Circuit 33 Simulation 3.5 NMOS Transistor 34 4 A PHYSICS BASED THRESHOLD 35 VOLTAGE MODELING 4.1 Introduction 35 4.2 Threshold Voltage Model 36 4.3 Short Channel Threshold Voltage Shift 40 4.4 Narrow Width Effects 41 ix 5 PHYSICALLY BASED MODEL FOR 44 EFFECTIVE MOBILITY FOR ELECTRON IN THE INVERSION LAYER 5.1 Introduction 44 5.2 Schwarz and Russek Mobility Model 44 5.3 Proposed Mobility Model 47 5.3.1 Phonon Scattering 52 5.3.2 Coulomb Scattering 52 5.3.3 Surface Roughness Scattering 53 6 A PHYSICALLY BASED COMPACT I-V 54 MODEL 6.1 Introduction 54 6.2 Short Channel I-V Model 55 6.3 Compact I-V Model 59 6.4 Source Drain Resistance 62 7 VELOCITY FIELD MODEL 64 7.1 Introduction 64 7.2 Velocity Saturation Region Length 63 7.3 A Pseudo 2D Model for Velocity 66 Saturation Region 8 RESULT AND DISCUSSION 70 8.1 Introduction 70 8.2 I-V Model Evaluation 70 8.3 Threshold Voltage 74 8.4 Doping Concentration Dependence 76 8.5 Temperature Dependence 79 8.6 Peak Field At The Drain 81 x 9 CONCLUSIONS AND 83 RECOMMENDATIONS 9.1 Summary and Conclusion 83 9.2 Recommendations 84 REFERENCES 86 APPENDICES A-G 92 - 107 xi LIST OF TABLES TABLE NO. TITLE PAGE 2.1 Approaches of Compact Modeling 15 2.2 BSIM SPICE Level 16 4.1 Values of α and β for various semiconductors 38 xii LIST OF FIGURES FIGURE NO. TITLE PAGE 1.1 Growth of transistor counts for Intel processors 2 accordance to Moore's Law 1.2 Feature Size Growth 2 1.3 MOSFET Source to Drain Cross Section 4 2.1 Drift velocity versus electric field in Silicon 11 2.2 Drift velocity versus electric field in for three 11 different semiconductor 2.3 Depiction of electrons density in channel under 12 electric field 2.4 Charges and their location in thermally oxidized 13 silicon 2.5 Post oxidation dangling bonds that will become 14 interfacial traps 2.6 Coordinate system used for the model derivation. 20 2.7 Comparison of I-V characteristic for a constant 20 mobility and for field-dependent mobility and velocity saturation effects. 2.8 Simplified Cross Section of Parasitic Resistance of 22 a NMOS 2.9 Hot Carrier Generation 23 2.10 Schematic cross section of “inside” and “outside” 24 LDD 2.11 A schematic diagram of half of a n-channel 25 MOSFET xiii 2.12 Cross-sectional images showing a strained-Si 26 MOSFET with a 25 nm gate length and its strained- Si layer 2.13 TEM micrographs of 45-nm p-type MOSFET 27 2.14 TEM micrographs of 45-nm n-type MOSFET 27 2.15 DI-LDD device cross section 28 2.16 Surface electric field at drain edge for conventional 28 and DI-LDD devices from 2D device simulation, VSUB = -1V and L=0.6 µm 3.1 Electrical Model Development Process 31 3.2 Running Basic Simulation Using Circuit 32 3.3 Parameter Extraction for Proposed Models 32 3.4 Schematic of an NMOS transistor 34 4.1 Metal-semiconductor work function difference 37 versus doping concentration for aluminum, gold, and n+ and p+ polysilicon gates 4.2 Charge sharing in the short channel threshold 40 voltage model 4.3 Cross section of an NMOS showing the depletion 42 region along the width of the device 4.4 Qualitative variation of threshold voltage with 43 channel length 4.5 Qualitative variation of threshold voltage with 43 channel width 5.1 Comparison of calculated and measured μeff versus 46 Eeff for several channel doping levels without Coulomb scattering and surface roughness scattering 5.2 Comparison of calculated and measured μeff versus 46 Eeff for several channel doping levels with Coulomb scattering and surface roughness scattering 5.3 Schematic diagram of Eeff and doping concentration 47 dependence of mobility in inversion layer by three dominant scattering mechanism xiv 5.4 A diamond structure with (100) lattice plane at 49 [100] direction 5.5 A diamond structure with (110) lattice plane at 50 [110] direction 5.6 A diamond structure with (111) lattice plane at 50 [111] direction