PROJECT: TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS FP7‐INFSO‐IST‐248789 DELIVERABLE D4.2.1 Report of the mechanisms devised to reconfigure each memory block Acronym TRAMS Project name Terascale Reliable Adaptive Memory Systems Grant agreement number 248789 Call FP7‐ICT‐2009‐4 Coordinator Universitat Politècnica de Catalunya (UPC) Partners University of Glasgow (UOG) Imec Intel Corporation Iberia Start date of the project 01.01.2010 Duration 36 months, until 31.12.2012 Project web site trams‐project.eu Document of the Workpackage WP4 Type of document and code Deliverable, D4.2 Document title Report of the mechanisms devised to reconfigure each memory block Date of preparation 15.01.2012 Authors Ramon Canal (UPC), Josep‐Llorenç Cruz (UPC) Responsible of the deliverable Ramon Canal Reviewed by Xavier Vera (Intel), Antonio Rubio (UPC) Target dissemination level Public Status of the project In progress Version 3.1 Document location trams‐project.eu/deliverables ; intranet Document history Version 1.0 Internal reviewing Version 2.0 Consortium reviewing Version 3.0 Submitted to EC © 2011 TRAMS Project Consortium, All Rights Reserved. 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Nothing contained in this document should be construed as granting by implication, any license or right to use any copyright without the express written consent of TRAMS. Table of Contents 1. Executive Summary ....................................................................................................................... 1 2. Introduction .................................................................................................................................. 1 3. Objectives and State‐of‐the‐art .................................................................................................... 2 4. Evaluation Framework .................................................................................................................. 4 5. Techniques under analysis ............................................................................................................ 4 5.1. Architectural Solutions ........................................................................................................... 4 5.1.1. High‐Performance Mode ..................................................................................................... 5 5.1.2. Design Issues: Low Voltages and Manufacturability ........................................................... 6 5.1.3. Low‐Power Working Behavior ............................................................................................. 7 5.1.4. Mode Changes ..................................................................................................................... 9 5.1.5. Timing Details ....................................................................................................................... 9 5.1.6. Results ................................................................................................................................ 10 6. Conclusions ................................................................................................................................. 15 7. References .................................................................................................................................. 17 8. Glossary ....................................................................................................................................... 19 TRAMS project, FP7‐INFSO‐IST‐248789 1. Executive Summary This deliverable describes the work done in Task 4.2. This task concentrates on memory reconfiguration strategies to cope with variability. At this time, we are focusing on cache redesign to take advantage of the analysis of WP2 and WP3. In essence, we evaluate the design and performance of hybrid SRAM‐DRAM cells to find the best trade‐off between performance (i.e. delay and power) and robustness to variability scenarios. Modern microprocessors use multiple power modes to exploit the trade‐off between performance and power. Low‐power modes rely on low frequencies and voltages to reduce the energy budget. However, manufacturing‐induced parameter variations make SRAM cells unreliable at supply voltages below Vccmin. Moreover, the probability of failure increases exponentially in such voltages. Recent proposals provide a small fault‐coverage due to their trade‐off between fault coverage for overhead, thus they are unsuitable for fault‐dominated future technology nodes. To deal with this shortcoming, we propose the Full Error Recovery (FER) fault‐tolerant cache, which combines SRAM and eDRAM cells in the L1 data cache to provide 100% fault coverage. An n‐way set‐associative FER cache implements one cache way with fast SRAM banks and the remaining ones with low‐power and reduced area eDRAM banks. The FER cache has been designed with two different operation modes: high‐performance and low‐power. In high‐ performance mode, the entire cache capacity is used, while in low‐power mode, eDRAM banks are used to keep replicas of SRAM banks. The proposal provides 100% fault‐coverage of defective cells (i.e. permanent faults), which is a major design concern for future technology nodes. 2. Introduction Most current microprocessors support multiple power modes to exploit the trade‐off between performance and power. In the high‐performance mode, the processor works at a high frequency together with a high voltage level to speed‐up the execution of the workload. In the low‐power mode, low frequency/voltage levels are used to improve energy savings. This mode is typically selected when the processor is idle or it has minimal workload. However, as transistor features continue shrinking in future technologies, parameter variations increase due to the imperfections in the semiconductor fabrication process. This makes memory semiconductor cells more unreliable at low voltages. If the voltage is lowered beyond a given reliable level, namely Vccmin, the probability of failure increases exponentially. This increase is due to the higher sensitivity of cell stability to parametric variations at low supply voltages. In cache memories, which occupy a large area in current microprocessors, the Vccmin of a given structure (e.g., L1 or L2 caches) is determined by the highest Vccmin of its memory cells. Moreover, as defective cells are randomly distributed through the processor, cache memories typically determine the Vccmin of the processor as a whole. Microprocessor caches have been typically implemented using fast SRAM cells. Nevertheless, a few years ago, eDRAM cells [1] were introduced in some modern microprocessors [2]. Although slower than SRAM cells, they improve storage density by a 3x to 4x factor and reduce energy. Nevertheless, eDRAM requires refresh operations to avoid capacitors to lose their state. Because page 1/19 TRAMS project, FP7‐INFSO‐IST‐248789 of each technology presents its advantages and shortcomings, recent works [2] [3] [4] propose to combine different semiconductor technologies to build high‐performance and energy efficient cache hierarchies. Process variation affects in a different way the different memory cell technologies. In SRAM cells, they induce static noise margin (SNM) variability which causes errors [5] [6] [7] in some cells when working below Vccmin. Different approaches have been devised to deal with this problem [8] [9] [10]. Basically, these solutions allow the system to work below Vccmin by disabling those segments of the cache where one or more bits can fail, thus reducing the effective storage capacity. eDRAM technology is also susceptible to device variations that basically lump into the cell retention time. The worst case of these device