Performance Characterization • Delay analysis • Transistor sizing • Logical effort • Power analysis ECE 261 James Morizio 1 Delay Definitions • tpdr: rising propagation delay – From input to rising output crossing VDD/2 • tpdf: falling propagation delay – From input to falling output crossing VDD/2 • tpd: average propagation delay – tpd = (tpdr + tpdf)/2 • tr: rise time – From output crossing 0.2 VDD to 0.8 VDD • tf: fall time – From output crossing 0.8 VDD to 0.2 VDD ECE 261 James Morizio 2 Simulated Inverter Delay • Solving differential equations by hand is too hard • SPICE simulator solves the equations numerically – Uses more accurate I-V models too! • But simulations take time to write 2.0 1.5 1.0 (V) t = 66ps t = 83ps V pdf pdr in V 0.5 out 0.0 0.0 200p 400p 600p 800p 1n t(s) ECE 261 James Morizio 3 Delay Estimation • We would like to be able to easily estimate delay – Not as accurate as simulation – But easier to ask “What if?” • The step response usually looks like a 1st order RC response with a decaying exponential. • Use RC delay models to estimate delay – C = total capacitance on output node – Use effective resistance R – So that tpd = RC • Characterize transistors by finding their effective R – Depends on average current as gate switches ECE 261 James Morizio 4 RC Delay Models • Use equivalent circuits for MOS transistors – Ideal switch + capacitance and ON resistance – Unit nMOS has resistance R, capacitance C – Unit pMOS has resistance 2R, capacitance C • Capacitance proportional to width • Resistance inversely proportional to width d s kC kC R/k d 2R/k d g k g kC g k g s kC kC kC s s d ECE 261 James Morizio 5 Example: 3-input NAND • Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). ECE 261 James Morizio 6 Example: 3-input NAND • Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). ECE 261 James Morizio 7 Example: 3-input NAND • Sketch a 3-input NAND with transistor widths chosen to achieve effective rise and fall resistances equal to a unit inverter (R). 2 2 2 3 3 3 ECE 261 James Morizio 8 3-input NAND Caps • Annotate the 3-input NAND gate with gate and diffusion capacitance. 2 2 2 3 3 3 ECE 261 James Morizio 9 3-input NAND Caps • Annotate the 3-input NAND gate with gate and diffusion capacitance. 2C 2C 2C 2C 2C 2C 2 2 2 2C 2C 2C 3C 3 3C 3C 3 3C 3C 3 3C 3C ECE 261 James Morizio 10 3-input NAND Caps • Annotate the 3-input NAND gate with gate and diffusion capacitance. 2 2 2 3 9C 5C 3 3C 5C 3 3C 5C ECE 261 James Morizio 11 Elmore Delay • ON transistors look like resistors • Pullup or pulldown network modeled as RC ladder • Elmore delay of RC ladder t pd ≈ Ri−to−sourceCi nodes i = R1C1 + (R1 + R2 )C2 + ... + (R1 + R2 + ... + RN )CN R1 R2 R3 RN C1 C2 C3 CN ECE 261 James Morizio 12 Example: 2-input NAND • Estimate worst-case rising and falling delay of 2- input NAND driving h identical gates. 2 2 Y A 2 h copies x B 2 ECE 261 James Morizio 13 Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 Y A 2 6C 4hC x h copies B 2 2C ECE 261 James Morizio 14 Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 Y A 2 6C 4hC x h copies B 2 2C R Y t = (6+4h)C pdr ECE 261 James Morizio 15 Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 Y A 2 6C 4hC x B 2 2C h copies R Y t = 6 + 4h RC (6+4h)C pdr ( ) ECE 261 James Morizio 16 Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 Y A 2 6C 4hC x h copies B 2 2C ECE 261 James Morizio 17 Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 Y A 2 6C 4hC h copies x B 2 2C R/2 x Y t = R/2 2C (6+4h)C pdf ECE 261 James Morizio 18 Example: 2-input NAND • Estimate rising and falling propagation delays of a 2-input NAND driving h identical gates. 2 2 Y A 2 6C 4hC x h copies B 2 2C t = 2C R + 6 + 4h C R + R x R/2 Y pdf ( )( 2 ) ( ) ⁄( 2 2 ) R/2 2C (6+4h)C = (7 + 4h) RC ECE 261 James Morizio 19 Delay Components • Delay has two parts – Parasitic delay • 6 or 7 RC • Independent of load – Effort delay • 4h RC • Proportional to load capacitance ECE 261 James Morizio 20 Contamination Delay • Best-case (contamination) delay can be substantially less than propagation delay. • Ex: If both inputs fall simultaneously 2 2 Y A 2 6C 4hC x B 2 2C R R Y t = 3+ 2h RC (6+4h)C cdr ( ) ECE 261 James Morizio 21 Diffusion Capacitance • We assumed contacted diffusion on every s / d. • Good layout minimizes diffusion area • Ex: NAND3 layout shares one diffusion contact – Reduces output capacitance by 2C – Merged uncontacted diffusion might help too 2C 2C Shared Contacted Diffusion Isolated Contacted 2 2 2 Merged Diffusion Uncontacted 3 7C Diffusion 3 3C 3C 3C 3C 3 3C ECE 261 James Morizio 22 Layout Comparison • Which layout is better? VDD VDD A B A B Y Y GND GND ECE 261 James Morizio 23 Resizing the Inverter Minimum-sized 2λ transistor: W=3λ, L=2λ To get equal rise and fall times, βn = βp Wp = 3Wn, assuming 3λ n-diffusion that electron mobility is three times that of holes poly Wp=9λ 2λ Sometimes the function being implemented 9λ p-diffusion makes resizing unnecessary! poly ECE 261 James Morizio 24 Analyzing the NAND Gate VDD βp1 1 βp2 βp3 a βn, eff = b c 1 + 1 + 1 F βn1 βn2 βn3 a βn1 Resistances are in series (conductances b β n2 are in parallel) c βn3 If βn1 = βn2 = βn3 = βn then βn, eff = βn/3 • Pull-down circuit has three times resistance, Why not consider reGsisntdances in parallel?one-third times the conductance For pull-up, only one transistor has to be on, βp, eff = min{βp1,βp2,βp3} If βp1 = βp2 = βp3 = βp = βn/3 then βn, eff = βp no resizing is necessary ECE 261 James Morizio 25 Analyzing the NOR Gate VDD 1 β = p, eff 1 a + 1 + 1 βp1 βp1 βp2 βp3 b βp2 Resistances are in series (conductances c are in parallel) βp3 βn1 If β = β = β = β then β = β /3 βn2 βn3 p1 p2 p3 p p, eff p a b c • Pull-up circuit has three times resistance, Gnd one-third times the conductance For pull-down, only one transistor has to be on, βn, eff = min{βn1,βn2,βn3} If βn1 = βn2 = βn3 = βn = 3βp then βn,eff=9βp,eff considerable resizing is necessary Wp = 9Wn! ECE 261 James Morizio 26 Effect of Series Transistors Diffusion Diffusion L poly poly L poly 3L L poly W W ECE 261 James Morizio 27 Effect of Series Transistors VDD Transistor resizing Resize the pull-up transistors to a example βp make pull-up times equal c βp b After resizing: βp a: 2βp, b: 2βp, c: βp Pull-down ECE 261 James Morizio 28 Transistor Placement (Series Stack) How to order transistors in a series stack? Body effect: δVt ∝ √Vsb • At time t = 0, a=b=c=0, f=1, capacitances are charged Pull-up • Ideally V = V = V 0.8V stack ta tb tc • However, V > V > V because of F ta tb tc a t body effect a Ca b • If a, b, c become 1 at the same time, which tb Cb transistor will switch on first? c • tc will switch on first (Vsb for tc is zero), Cc will Cc discharge, pulling Vsb for tb to zero tc • If signals arrive at different times, how should the Gnd transistors be ordered? • Design strategy: place latest arriving signal nearest to output-early signals will discharge internal nodes ECE 261 James Morizio 29 Transistor Placement Pull-up stack 2 a F 2 ta C 2 a 2 tb b Cb c Primary Cc Pull-up t inputs c stack (change Gnd 2 2 b simultaneously) 2 ta C F 2 a tb a Cb c Cc tc ECE 261 James Morizio 30 Some Design Guidelines • Use NAND gates (instead of NOR) wherever possible • Placed inverters (buffers) at high fanout nodes to improve drive capability • Avoid use of NOR completely in high-speed circuits: A1 + A2 + … + An = A1.A2….An ECE 261 James Morizio 31 Some Design Guidelines • Use limited fan-in (<10): high fan-in long series stacks • Use minimum-sized gates on high fan-out nodes: minimize load presented to driving gate ECE 261 James Morizio 32 Logical Effort • Chip designers face a bewildering array of choices ? ? ? – What is the best circuit topology for a function? – How many stages of logic give least delay? – How wide should the transistors be? • Logical effort is a method to make these decisions – Uses a simple model of delay – Allows back-of-the-envelope calculations – Helps make rapid comparisons between alternatives – Emphasizes remarkable symmetries ECE 261 James Morizio 33 Example • Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded automotive processor.