3.3.3 Computer Architecture VON NEUMANN ARCHITECTURE (SISD) 1 FLYNN’S TAXONOMY 1 THE COMPONENTS OF THE CPU 2 CONTROL UNIT - CU 3 ARITHMETIC AND LOGIC UNIT - ALU 3 INCREMENTER 3 THE REGISTERS OF THE CPU 4 MEMORY ADDRESS REGISTER – MAR 4 MEMORY DATA REGISTER – MDR 4 PROGRAM COUNTER – PC 4 CURRENT INSTRUCTION REGISTER – CIR 4 STATUS REGISTER – SR 5 INTERRUPT LINES 5 GENERAL PURPOSE REGISTERS 5 THE FETCH EXECUTE CYCLE 6 FETCH EXECUTE AND INTERRUPTS 7 SPEEDING UP CPU OPERATION 9 CACHE MEMORY 9 PIPELINES/PIPELINING 10 CO-PROCESSORS 11 Created by E Barwell Sept 2009, rev Sep 2011 OTHER PROCESSOR ARCHITECTURES 12 MULTIPLE PROCESSORS (PARALLEL PROCESSING – MIMD) 12 ARRAY PROCESSORS (VECTOR PROCESSORS - SIMD) 13 ALGORITHMS TO TAKE ADVANTAGE OF NON- VON NEUMANN ARCHITECTURES 13 COMPUTER ARCHITECTURES - REMINDER 13 SISD 13 SIMD 13 MISD 13 MIMD 13 CISC AND RISC PROCESSORS 14 CLOCK SPEEDS 14 CISC - COMPLEX INSTRUCTION SET COMPUTER 15 RISC - REDUCED INSTRUCTION SET COMPUTER 15 Created by E Barwell Sept 2009, rev Sep 2011 3.3.3 Computer architecture 1 Von Neumann architecture (SISD) Is the term used to describe the classical CPU structure which has the following components, which involves a stored program computer: (Alan Turing proposed a similar structure earlier in the 1930’s but this got looked over during the build up to the war). Separate memory containing both program code and data Program code and data stored in the same format Single control unit to manage execution of instructions Instructions executed in sequential manner (one after another) There is a bottleneck caused by not being able to fetch instructions and perform data operations at the same time. This is known as a SISD architecture as we have single instructions working on single pieces of data one after the other Flynn’s Taxonomy This is one of 4 basic architecture designs known collectively as “Flynn’s Taxonomy” – proposed by Michael Flynn in 1966. SISD SIMD (Single Instruction stream/ Single Data stream) (Single Instruction stream/Multiple Data streams) Classic Von Neumann, execute one instruction at a The instruction stream is applied to each of the data time manipulating a single piece of data at a time. A streams. Instances of the same instruction can run in single core processor system. parallel on multiple cores, servicing different data streams. Array or Vector processor processing multiple items of data with a single instruction (arrays and matrices). MISD MIMD (Multiple Instruction streams/Single Data stream) (Multiple Instruction streams/Multiple Data streams) Multiple instruction streams can be applied in parallel On a multicore computer, each instruction stream runs to a single data source. Could be used for running on a separate processor with independent data. This is decryption routines on a single data source. the current model for multicore personal computers and has been used for years on Super Computer systems. Created by E Barwell Sept 2009, rev Sep 2011 3.3.3 Computer architecture 2 The Components of the CPU The CPU (Central Processing Unit) or processor is the heart of any computer system. Its only task is to repeatedly fetch machine instructions (machine code) from memory and execute them. External events happen, which can alter the order in which instructions are executed (Interrupts which we will look at later). We program the CPU using machine code. CPU’s are categorised by the width (in bits) of their Data Bus known as the word length CPU with 8 Bit Data Bus, called an 8 Bit CPU (e.g. Z80, Amstrad, 6502, C64, BBC) CPU with 16 Bit Data Bus, called a 16 Bit CPU (e.g. 68000 – Atari ST, Amiga, MegaDrive) CPU with 32 Bit Data Bus, called a 32 Bit CPU (e.g. 68040, Pentium) CPU with 64 Bit Data Bus, called a 64 Bit CPU (e.g. AMD 64) Below is a schematic of a standard CPU (shown inside the dotted line). Interrupt Lines ( 1 way) CENTRAL PROCESSING UNIT REGISTERS General Purpose ALU SR Arithmetic & Logic Unit Status Register r0, r1, r2 etc... ACCUMULATORS Incrementer CIR PC Current Instruction Register Program Counter CU MDR MAR Memory Data Control Unit Memory Address Register Register ) y ) a y a w d k e c w 1 t ( s o c t 2 l e ( n S C n e S U n l n o a B o U c n p B S r s m S e u A t o E B x c T l R l E l A o D a r D t D o n t A o C RANDOM ACCESS MEMOR Y [MAIN STORE ] Created by E Barwell Sept 2009, rev Sep 2011 3.3.3 Computer architecture 3 Control Unit - CU Often referred to as “The Brain of the CPU”, it controls the operation of the CPU. Receives timing information from an external clock (quoted in MHz/GHz) In general the faster the clock the faster the CPU can execute instructions Controls the Fetch – Execute cycle. Generates signals along the Control Bus to order other parts of the CPU, to do things. These include signals to: Initiate Memory Transfers (move data to and from the CPU) Control other components of CPU such as ALU and Incrementer Transfer data between internal components/registers of the CPU Perform decoding of current instruction Check Status Register for Interrupts, take action if present Arithmetic and Logic Unit - ALU Responsible for performing calculations (adding, subtracting, multiplication), logical operations (And, Or, Not) and comparisons (comparing one value with another) When an arithmetic instruction is encountered, control is transferred to the ALU for execution Uses its own registers known as Accumulators, which hold the results of calculations The basic outcomes of the results (is the result zero or negative) of calculations are stored in the CCR (or status register) Incrementer Sole job is to increase the value of the Program Counter during the Fetch – Execute cycle. Basically a separate (simple) ALU just to add to or subtract values from the PC Created by E Barwell Sept 2009, rev Sep 2011 3.3.3 Computer architecture 4 The Registers of the CPU A register is a storage area inside the CPU. They are in general the same width as the Data Bus. They are dedicated storage areas that work at the same speed as the CPU (unlike RAM) and help the CU keep track of important values. On the next few pages are descriptions of the role and functions of the standard ones. Memory Address Register – MAR Placing an address in the MAR selects that memory location It is the same width (same number of bits) as the CPU’s Address Bus Memory Data Register – MDR Also known as Memory Buffer Register – MBR – You must remember this Is connected directly to the Data Bus It is the same width (same number of bits) as the Data Bus When reading data from memory the following happens inside the CPU The memory address of the data is placed in the MAR The CU initiates a memory transfer from RAM to CPU (read cycle) using the Data Bus The data arrives at the CPU and is stored in the MDR. When writing data to memory the following happens inside the CPU The memory address where the data is to be stored is placed in the MAR The data to be written to memory is placed in the MDR by the CU. The CU initiates a memory transfer from CPU to RAM (Write cycle) using the Data Bus Program Counter – PC Also known as Sequence Control Register – SCR – You must remember this. Holds the memory address of the next instruction to execute The PC is the same size as the MAR (and hence the Address Bus) Current Instruction Register – CIR Holds the machine code instruction the CPU is currently processing When a new instruction is fetched from RAM it is transferred from the MDR to the CIR Once the instruction is in the CIR the CU can decode and execute it Holding the instruction in the CIR allows more data to arrive (to be used by the instruction) at the MDR without overwriting the current instruction Created by E Barwell Sept 2009, rev Sep 2011 Status Register – SR Keeps track of the basic results of operations performed by the ALU Results are stored as a series of flags (bits), which can be interrogated individually Bits are set (1) or cleared (0) depending upon the ALU results Flags can be either true or false and thus be represented by a single Bit. If bit is clear/zero then the flag is false If bit is set/one then the flag is true There are four common Flags/Bits inside the SR Flag Name Purpose Z bit Zero Set if result of an instruction was Zero N bit Negative Set if result of an instruction was Negative C bit Carry Set if result of an instruction generated a Carry V bit Overflow Set if result of an instruction was too large to hold in the Accumulator (the number needed more bits that the accumulator has) The flags are used to make decisions When comparing 2 values the ALU effectively subtracts them. If they are equal the result would be Zero and the Z flag would be set. If one was bigger than the other then the N would be set or cleared (depending on which was the biggest) Interrupt Lines Signals from other devices (chips) or software, that are requesting CPU resource (time) Set various bits (depending on priority level of particular interrupt) in the Status Register At the end of each Fetch-Execute cycle, the Status register is checked to determine if any interrupts occurred The CPU will clear the relevant bit in the Status Register, save its state (to resume later) and look up the relevant interrupt vector (effectively the memory address of a program that knows what to do with a particular interrupt) to deal with this interrupt General Purpose Registers Can be used to store intermediate values without the need to access RAM Old 8-bit CPU’s only have one ACC available but modern CPU’s use lots (16+) of general-purpose registers that can be used for the same purpose Helps speed up program execution as values can be held in registers rather than held in to memory.