Purdue University Purdue e-Pubs Open Access Dissertations Theses and Dissertations January 2014 Scaling Issues and Solutions in Ultra Scaled MOSFETs using Predictive Modeling Mehdi Salmani Jelodar Purdue University Follow this and additional works at: https://docs.lib.purdue.edu/open_access_dissertations Recommended Citation Salmani Jelodar, Mehdi, "Scaling Issues and Solutions in Ultra Scaled MOSFETs using Predictive Modeling" (2014). Open Access Dissertations. 1504. https://docs.lib.purdue.edu/open_access_dissertations/1504 This document has been made available through Purdue e-Pubs, a service of the Purdue University Libraries. Please contact [email protected] for additional information. *UDGXDWH6FKRRO)RUP30 5HYLVHG 0814 PURDUE UNIVERSITY GRADUATE SCHOOL Thesis/Dissertation Acceptance 7KLVLVWRFHUWLI\WKDWWKHWKHVLVGLVVHUWDWLRQSUHSDUHG %\ Mehdi Salmani Jelodar (QWLWOHG Scaling Issues and Solutions in Ultra Scaled MOSFETs using Predictive Modeling Doctor of Philosophy )RUWKHGHJUHHRI ,VDSSURYHGE\WKHILQDOH[DPLQLQJFRPPLWWHH GERHARD KLIMECK PEIDE YE MARK S. LUNDSTROM KWOK K. NG To the best of my knowledge and as understood by the student in the Thesis/Dissertation Agreement, Publication Delay, and Certification/Disclaimer (Graduate School Form 32), this thesis/dissertation adheres to the provisions of Purdue University’s “Policy on Integrity in Research” and the use of copyrighted material. GERHARD KLIMECK $SSURYHGE\0DMRU3URIHVVRU V BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB $SSURYHGE\ M. R. Melloch 12/09/2014 +HDGRIWKHDepartment *UDGXDWH3URJUDP 'DWH SCALING ISSUES AND SOLUTIONS IN ULTRA SCALED MOSFETS USING PREDICTIVE MODELING A Dissertation Submitted to the Faculty of Purdue University by Mehdi Salmani-Jelodar In Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy December 2014 Purdue University West Lafayette, Indiana ii To my parents and my sisters. iii ACKNOWLEDGMENTS I would like to express my gratitude to my advisor, Professor Gerhard Klimeck, for the valuable insights he provided for this research and his continous support of my PhD. I would like to thank him for providing all the necessary computing resources. He introduced me to the world of high performance computing and its applications, the problem solving in Physics and Engineering, which will be an invaluable experi- ence for my future career pursuits. I would also like to thank Dr. K. Ng, Professor M. Lundstrom and Professor P. Ye for serving on my advisory committee. I am grateful to Hesam Ilati, Matthias Tan, Tarek Amin, Saumitra Mehrotra and Dr. Sebastian Steiger as great friends and colleagues for their supports and help in life, education and research. Also, I am thankful to Dr. SungGeun Kim, Prof. Mathieu Luisier, Yaohua Tan, Dr. Abhijeet Paul, Daniel Mejia, Dr. Ganesh Hegde, Dr. Seung Hyun Park, Dr. Parijat Sengupta, Dr. Sunhee Lee, Zhengping Jiang, Daniel Valencia for stimulating discussions. I would also like to thank our current NEMO5 team Dr. Jim Fonseca, Dr. Bozidar Novakovic, Prof. Michael Povolotsky, Prof. Tillman Kubis who have been of great support. I would like to thank all my colleagues from the NCN and the Klimeck group for providing a stimulating and fun environment in which to learn and grow. I also would like to special thanks to NCN staff members Megan Rush, Vicki Johnson, Cheryl Haines, Amanda Buckles and Leslie Schumacher for their help over the last six years. Outside of my office, I always had very strong support from my wonderful friends, including Behtash Behin-aein, Nichole Ramirez, Ali Jalali, Trinity Overmyer, Ali Jahanian, Sofia Singlton, Alicia English, Behtrooz Jalalahmad, Alicia Philips, Teimor Maleki, Lars Suderland, Golsa Moaieri, Ali Ahmadian, Ali Razavieh and Sebastian Feste. Lastly, and most importantly, I wish to thank my parents and family for their unconditional love and support. iv TABLE OF CONTENTS Page LIST OF TABLES ................................ viii LIST OF FIGURES ............................... ix ABSTRACT ................................... xv 1 INTRODUCTION .............................. 1 1.1 Semi-empirical Model Development .................. 3 1.2 CMOS Transistor Roadmap Projection ................ 6 1.3 Design Guidelines for ultra-scaled MOSFETs (Lch <12 nm) ..... 8 1.4 Optimum High-k Oxide for the Best Performance in Ultra-scaled MOS- FETs ................................... 9 1.5 Quantum Confined SiGe MOSFETs .................. 10 1.6 Thesis Organization ........................... 11 2 SEMI-EMPIRICAL MODEL DEVELOPMENT .............. 12 2.1 Introduction ............................... 12 2.2 Lattice Dynamics and the Valence Forced Field Method ....... 14 2.2.1 Valence Force Field Model of the Crystal Energy ...... 14 2.2.2 Elastic Constants ........................ 16 2.2.3 Lattice Dynamics and Phonons ................ 16 2.3 Genetic Algorithm ........................... 17 2.3.1 Standard Genetic Algorithm .................. 18 2.3.2 Parallel Genetic Algorithm ................... 20 2.4 Phonon Dispersion for GaAs ...................... 20 2.4.1 Fitness Function and PGA Parameters ............ 21 2.4.2 Predictiveness of the model .................. 23 2.4.3 Extending the model for other materials: InAs ........ 23 v Page 2.5 An application of the EVFF model in thermoelectricity ....... 23 2.6 Conclusion ................................ 24 3 CMOS TRANSISTOR SCALING ROADMAP ............... 29 3.1 Introduction ............................... 29 3.2 Methodology .............................. 30 3.2.1 Maximum tolerable series resistance calculation for HPdevices 34 3.3 Simulations and results ......................... 35 3.4 Discussion ................................ 37 3.4.1 Short Channel Effects (SCEs) ................. 37 3.4.2 Source-to-drain Tunneling ................... 38 3.4.3 Quantum Confinement ..................... 39 3.5 Conclusion ................................ 40 4 DESIGN GUIDELINES FOR TUNNELING DOMINANT REGIME MOS- FETS (LCH<12 NM) ............................. 42 4.1 Methodology .............................. 43 4.2 Results and Discussion ......................... 46 4.3 Conclusion and Future Work ...................... 50 5 SILICON GERMANIUM BASED MOSFETs ............... 52 5.1 Introduction ............................... 52 5.2 Methodology .............................. 55 5.3 Results and Discussion ......................... 57 5.4 Conclusion ................................ 60 6 SUMMARY AND FUTURE WORK .................... 62 6.1 Semi-empirical Model Development .................. 62 6.2 CMOS Transistor Scaling Roadmap .................. 63 6.3 Design Guidelines for ultra-scaled MOSFETs ............. 63 6.4 Guidelines for High-K Gate Stack Design ............... 67 6.5 Quantum Confined SiGe-based MOSFETs .............. 69 vi Page REFERENCES .................................. 70 A Agreement on Reusing Published Papers .................. 78 B Publication List ................................ 86 VITA ....................................... 89 vii LIST OF TABLES Table Page 3.1 ITRS-PIDS table for High-Performance(HP) Devices. Will be available online at ITRS website by Jan 2013. ................... 31 4.1 Examples to engineer m∗ of Si (bottom of CB for NMOS and top of VB for PMOS) for 5x5 nm2 square cross-section NWs. For NMOS (PMOS), tensile (compressive) strain can reduce the m∗. For example for PMOS with compressive strain in 5th row the m∗ is less than the case of without any strain in the 4th row. ......................... 50 5.1 These values are calculated energy level for TVB for the cladding part. TVB values for the Si fin is almost at 0 meV . .............. 56 viii LIST OF FIGURES Figure Page 1.1 The Intel MOSFET scaling trend from 2005. Multiple innovations pushed the CMOS scaling this far and more innovations are needed to push the scaling further down to 5 nm and beyond. Number of atoms along the gate length (node atoms) and the gate width in FinFETs (critical atoms) and number of electrons in the channel are shown. These numbers are scaled down to a few atoms and electrons, which are not possible to accurately model with conventional drift diffusion or compact models. The image is adapted from [8]. .............................. 2 1.2 Scaling effects on number of atoms and electrons. (A) Shows the number of electrons under the gate based on ITRS [9] and Intel’s published data CG as NumberOfElectrons = (VDD VT ) q , where VDD, VT , CG and q are the supply voltage, the threshold− voltage,× the gate capacitance and electron charge, respectively. (B) Shows scaling of minimum feature size in CMOS technology based on Intel and ITRS roadmap data. ..... 3 1.3 Schematic description of the change in the electronic band structure (a) < 100 > and (b) < 110 > oriented Si nanowire under no-strain and compressive-strain conditions. ∆2 and ∆4 has 0.19 m0 and 0.91 m0 effec- tive masses, respectively. Orientation and strain both can vary band struc- ture and the effective mass at the bottom (top) of conduction (valance) band; consequently, the material behavior in MOSFET devices. .... 4 1.4 On the left, the flowchart shows MASTAR’s inputs and outputs. MAS- TAR gets SS and DIBL form recent devices [17]. Therefore, the calcula- tions are very dependent to the recent fabricated MOSFETs. It can have huge discrepancy over years. Specially, for far future it cannot capture the critical physics like quantum confinement and source to drain tunneling. Current MASTAR model lacks important physics, which leads to inaccu- rate projection for even near future