Rochester Institute of Technology RIT Scholar Works Theses 12-2019 Design of an Efficient Design forest T (DFT) Architecture and it's Verification Using Universal Verification Methodology Sushmitha Mavuram [email protected] Follow this and additional works at: https://scholarworks.rit.edu/theses Recommended Citation Mavuram, Sushmitha, "Design of an Efficient Design forest T (DFT) Architecture and it's Verification Using Universal Verification Methodology" (2019). Thesis. Rochester Institute of Technology. Accessed from This Master's Project is brought to you for free and open access by RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. DESIGN OF AN EFFICIENT DESIGN FOR TEST (DFT) ARCHITECTURE AND IT’S VERIFICATION USING UNIVERSAL VERIFICATION METHODOLOGY by Sushmitha Mavuram GRADUATE PAPER Submitted in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE in Computer Engineering Approved by: Mr. Mark A. Indovina, Graduate Research Advisor Senior Lecturer, Department of Electrical and Microelectronic Engineering Dr. Marcin Lukowiak, Committee Member Professor, Department of Computer Engineering Dr. Amlan Ganguly, Department Head Professor, Department of Computer Engineering DEPARTMENT OF COMPUTER ENGINEERING KATE GLEASON COLLEGE OF ENGINEERING ROCHESTER INSTITUTE OF TECHNOLOGY ROCHESTER,NEW YORK DECEMBER, 2019 I dedicate this work to my mother Surekha, my father Jithender and my friends, for their support and encouragement throughout my master’s program at Rochester Institute of Technology. Declaration I hereby declare that all the contents of this graduate project paper are original, except where specific references are made to the work of others. They are not submitted in part orinwhole to any other qualification or degree or University. The research work on the Design-verification of the DFT architecture is the result of my own work and it does not include any collaboration, except where specifically mentioned in the paper. Sushmitha Mavuram December, 2019 Acknowledgements I would like to thank my advisor Professor Mark A. Indovina for his support, guidance, en- couragement and feedback throughout the graduate project. I would like to thank Department of Computer Engineering, especially Dr. Ganguly, Dr. Kwasinski, and Dr. Lukowiak for their support throughout my Master’s program at Rochester Institute of Technology. Abstract The complexity of the circuit design has been significantly increased from 1980’s till date, and until 80’s, due to less complexity and technology node being down to 180nm, the need for Design for Test (DFT) equipment was not as important. The few System on Chips (SoC) were tested using test patterns sent from the external test equipment. As the technology node shrunk further, the devices became faster and the complexity of S0C’s increased as the chip could accommodate more transistors. The SoC’s have become more vulnerable to physical defects. Quality factor became a major issue, which pushed the industry standard of the test coverage very high i.e. between 98% to 100%. To achieve such a high test coverage, testing the SoC’s by external test equipment demands high test time and test cost. Due to this reason, the DFT architectures within the chip have become popular demand in the industry. With the DFT architectures like Memory-Built In Self Test (MBIST) and Logic- Built In Self Test (LBIST), the memories and core logic embedded in the chip will undergo self test at the speed of functional clock and hence saving test time and test cost. Introducing DFT into the chip implies increase in area due to overhead and increase in power consumption due to additional pins. So, the DFT architectures need to be efficient. This project paper discusses about designing an efficient DFT architecture on SoC by integrating MBIST and LBIST with JointTest Action Group-Test Access Port (JTAG-TAP) Controller and verifying using SysteVerilog (SV) and Universal Verification Methodologies (UVM) libraries. Detailed discussion of the design architecture and verification plan is included in the upcoming sections. Contents Contents v List of Figuresx 1 Introduction1 1.1 Design For Testability . .1 1.1.1 What is Built-In-Self-Test (BIST)? . .1 1.1.2 Need for BIST . .2 1.1.3 Important considerations while implementing BIST . .2 1.1.4 Importance of Joint-Test-Action-Group (JTAG) in testing . .2 1.2 Organization of the project paper . .3 2 Bibliographical Research5 2.1 Concepts in Design for Testability . .5 2.2 Design Verification . .6 2.3 Coverage driven Verification plan (CDV) . .6 2.4 Assertion based Verification plan (ABV) . .7 3 System Verification using Universal Verification Methodology (UVM)9 3.1 UVM Overview . .9 Contents vi 3.2 UVM Class Hierarchy . 10 3.2.1 UVM Testbench . 10 3.2.2 UVM Test . 11 3.2.3 UVM Environment . 11 3.2.4 UVM Agent . 11 3.2.5 UVM Sequence item . 12 3.2.6 UVM Sequence . 12 3.2.7 UVM Sequencer . 12 3.2.8 UVM Driver . 12 3.2.9 UVM Monitor . 13 3.2.10 UVM Scoreboard . 13 3.3 UVM Phases . 13 3.3.1 UVM Build Phase . 13 3.3.2 UVM Run Phase . 14 3.3.3 UVM Cleanup Phase . 14 3.3.4 UVM Debug . 14 4 Joint Test Action Group (JTAG) 15 4.1 JTAG Architecture . 16 4.1.1 JTAG Components . 16 4.1.2 Test Access Port (TAP) . 16 4.1.3 TAP Controller . 18 4.1.4 JTAG registers . 20 4.1.4.1 Bypass Register (DR) . 20 4.1.4.2 Boundary scan register (DR) . 20 Contents vii 4.1.4.3 IDCODE register (DR) . 23 4.1.4.4 Device specific/Internal registers (DR) . 23 4.1.4.5 Instruction register (IR) . 23 4.2 JTAG instructions . 24 4.2.1 EXTEST . 25 4.2.2 BYPASS . 25 4.2.3 SMAPLE/PRELOAD . 27 4.3 Design requirements of JTAG-TAP controller . 27 5 Memory-Built-In-Self-Test (MBIST) 30 5.1 BIST overview . 30 5.2 Types of faults to test for the memory . 31 5.3 Algorithm for detecting faults . 33 5.4 MBIST design requirements . 34 5.5 MBIST Architecture . 35 5.5.1 Design and working of MBIST components . 36 6 Logic-Built-In-Self-Test (LBIST) 39 6.1 LBIST overview . 39 6.2 LBIST Architecture . 39 6.2.1 LBIST Components . 40 6.2.2 LBIST Control signals and data signals . 41 6.3 LBIST design . 43 7 Integration of the lower level modules to form System on Chip design. 44 7.1 JML overview . 44 Contents viii 7.2 JML Architecture . 45 7.3 JML Operation . 46 8 UVM Verification architecture for JML 50 8.1 Components in the UVM Testbench . 50 8.1.1 JML Interface . 50 8.1.2 JML Environment . 50 8.1.3 JML Scoreboard . 52 8.1.4 JML Active_agent . 52 8.1.5 JML Passive_agent . 52 8.1.6 JML Sequence . 53 8.1.7 JML Transaction_in . 53 8.1.8 JML Driver . 53 8.1.9 JML Monitor_in . 53 8.1.10 JML Monitor_out . 54 8.1.11 JML Test . 54 8.1.12 JML Testbench top . 54 9 Results 55 9.1 Selection of MBIST and LBIST through TAP controller . 55 9.2 MBIST operation result . 56 9.2.1 Memory pass scenario . 57 9.2.2 Memory fail scenario . 57 10 Conclusion 59 10.1 Future Work . 60 Contents ix References 61 I Source Code I-1 I.1 RTL design (JML) . I-1 I.1.1 JML Top . I-1 I.1.2 JTAG-TAP Defines . I-7 I.1.3 JTAG-TAP . I-8 I.1.4 MBIST . I-30 I.1.5 Memory Model . I-52 I.2 Verilog Testbench - JML Top . I-55 I.3 UVM Testbench - JML Top . I-67 I.3.1 Interface . I-67 I.3.2 Sequencer . I-69 I.3.3 Driver . I-78 I.3.4 Monitor_in . I-85 I.3.5 Monitor_out . ..