iDragon SCX501 Programming Manual Release A May 9, 2000 RiSE Technology Company 1/193 Information provided is believed to be accurate and reliable. However, RiSE Technology assumes no responsibility for the consequences of use of such information nor for any infringements of patents or other rights of third parties which may result from its use. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 2/193 Release A RiS TM and iDragon TM are trademark of RiSETM Technology. All other trademarks are properties of respective owners. This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change with out notice. TABLE OF CONTENTS 1 TABLE OF CONTENTS 1 TABLE OF CONTENTS . .3 2 LIST OF TABLES . ..7 3 LIST OF FIGURES . .9 4. INTRODUCTIO . .11 5. HOW TO USE THIS MANUAL . .13 5.1 INTRODUCTION . .13 5.2 SPECIFIC NOTES . .13 5.3 ISSUING NOTES . .14 6 LIST OF REGISTERS . .15 7. SDRAM Controller . .27 7.1 INTRODUCTION . .27 7.2 MEMORY CONTROLLER . .27 7.3 MEMORY ADDRESS MAP . .27 7.4 IO ADDRESS MAP . .31 7.5 CACHE RELATED REGISTERS . .32 7.6 ADDRESS DECODE RELATED REGISTERS . .33 7.7 HOST SDRAM CONTROLLER REGISTERS . .36 7.8 SDRAM CONTROLER REGISTER ACCESS . .38 7.9 MEMORY CLOCK REGISTERS . .38 7.10 SDRAM INTERFACE . .40 7.11 SDRAM ARBITRATION: . .44 8. PCI CONTROLLERS . .45 8.1 INTRODUCTION . .45 8.2 METHOD FOR ACCESSING THE PCI CONFIGURATION REGISTERS . .46 8.3 CONFIGURATION ADDRESS REGISTER IO CF8H (CONFIG_ADDRESS) . .47 8.4 CONFIGURATION DATA REGISTER IO CFCH (CONFIG_DATA) . .47 3/193 Release RiSETM and iDragon TM are trademark of RiSETM Technology. All other trademarks are properties of respective owners. This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change with out notice. TABLE OF CONTENTS 8.5 THE NORTH BRIDGE CONFIGURATION REGISTERS . .48 8.6 THE SOUTH BRIDGE . .51 8.7 SOUTH BRIDGE PCI FUNCTION 0 CONFIGURATION REGISTERS . .52 8.8 SOUTH BRIDGE PCI FUNCTION 1 CONFIGURATION REGISTERS . .54 9. ISA INTERFACE . .63 9.1 INTRODUCTION . .63 9.2 PCI / ISA CYCLES . .64 9.3 XBUS READ AND WRITE . .67 9.4 FAST CPU RESET AND FAST GATE A20 . .68 9.5 ISA STANDARD REGISTERS . .69 9.6 ISA CONFIGURATION REGISTERS . .75 10. IDE CONTROLLER . .81 10.1.INTRODUCTION . .81 10.2.PRD TABLE ENTRY . .82 10.3.IDE BUS MASTER REGISTERS . .83 10.4.BUS MASTER IDE REGISTER DESCRIPTION . .83 10.5.BUS MASTER IDE COMMAND REGISTER . .84 10.6.OPERATION . .85 10.7.DATA SYNCHRONIZATION . .85 10.8.ERROR CONDITIONS . .86 10.9.PCI SPECIFICS . .86 11. VGA CONTROLLER . .87 11.1 INTRODUCTION . .87 11.2 VGA CONTROLLER . .87 11.3 VGA REGISTERS . .87 11.4 GENERAL VGA REGISTERS . .88 11.5 VGA SEQUENCER REGISTERS . .90 4/193 Release A RiSETM and iDragon TM are trademark of RiSETM Technology. All other trademarks are properties of respective owners. This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change with out notice. TABLE OF CONTENTS 11.6 GRAPHICS CONTROLLER REGISTERS . .92 11.7 ATTRIBUTE CONTROLLER REGISTERS . .95 11.8 CRT CONTROLLER REGISTERS . .97 11.9 VGA EXTENDED REGISTERS . .103 11.10ADDITIONAL MODES . .112 11.11INTERLACED MONITOR SUPPORT . .112 11.12RAMDAC REGISTERS . .113 11.13DCLK CONTROL REGISTERS . .114 12. GRAPHICS ENGINE . .117 12.1 INTRODUCTION ..