One stage of GAL16V8 in GAL Architecture combinational mode The Generic Array Logic device (GAL) is a PAL-type PLD structure comprising a programmable AND array followed by output logic macrocells (OLMC) that provide the versatility. Each OLMC provides a D latch, programmable polarity, output feedback to the fuse array and tri-state output control. One stage of GAL16V8 in Two-pass logic registered mode Example: Y1 = A + B D Q Y2 = A + B + Z Q' Observe that: Y2 = Y1 + Z CPLD Architecture The Altera 3032 is an example of a “Complex Programmable Logic Device” (CPLD). Compared with the GAL structure: – it contains more gates (typically 1000 to 20000) – it has more I/O pins – it is more versatile (much more complex logic equations may be implemented) 1 PAL-like block (details not shown) I/O block PAL-like PAL-like block block I/O block PAL-like block Interconnection wires D Q I/O block D Q PAL-like PAL-like block block I/O block D Q Figure 3.32 Structure of a CPLD Figure 3.33 A section of a CPLD Select Enable FPGA Architecture f 1 Flip-flop The Altera FLEX 10K is an example of a D Q “Field-Programmable Gate Array” (FPGA). Clock Compared with the GAL & CPLD structures: – it contains MANY more gate equivalents (typically > 100 000) To AND plane – it has more I/O capability – it is based on an highly interconnected array of Look-Up Table (LUT) logic blocks Figure 3.29 Output circuitry x 1 Logic block Interconnection switches 0/1 I/O block 0/1 x x f f 1 2 1 0/1 0 0 1 0 1 0 0/1 1 0 0 x 2 1 1 1 I/O block (a) Circuit for a two-input LUT (b) f 1 = x 1 x2 + x 1 x 2 x1 I/O block 1 0 f 1 0 1 x I/O block 2 (c) Storage cell contents in the LUT Figure 3.35 Structure of an FPGA Figure 3.36 A two -input lookup table 2 x1 x2 Select 0/1 0/1 0/1 Out Flip-flop 0/1 In 1 f 0/1 In 2 LUT D Q In 0/1 3 0/1 Clock 0/1 x3 Figure 3.37 A three-input LUT Figure 3.38 Inclusion of a flip-flop with a LUT x 3 f x 1 x1 0 x 2 0 0 f 1 f 0 1 0 2 x x x 2 2 1 3 0 f 1 0 1 f 1 f 2 1 Figure 3.39 A section of a programmed FPGA 3.