Intel® Quartus® Prime Standard Edition User Guide Debug Tools Updated for Intel® Quartus® Prime Design Suite: 18.1 Subscribe UG-20182 | 2018.09.24 Send Feedback Latest document on the web: PDF | HTML Contents Contents 1. System Debugging Tools Overview................................................................................. 7 1.1. System Debugging Tools Portfolio............................................................................ 7 1.1.1. System Debugging Tools Comparison........................................................... 7 1.1.2. Suggested Tools for Common Debugging Requirements.................................. 8 1.1.3. Debugging Ecosystem................................................................................ 9 1.2. Tools for Monitoring RTL Nodes.............................................................................. 10 1.2.1. Resource Usage....................................................................................... 10 1.2.2. Pin Usage............................................................................................... 12 1.2.3. Usability Enhancements............................................................................ 12 1.3. Stimulus-Capable Tools.........................................................................................13 1.3.1. In-System Sources and Probes.................................................................. 14 1.3.2. In-System Memory Content Editor..............................................................14 1.3.3. System Console.......................................................................................15 1.4. Virtual JTAG Interface Intel FPGA IP....................................................................... 15 1.5. System-Level Debug Fabric................................................................................... 16 1.6. System Debugging Tools Overview Revision History.................................................. 16 2. Analyzing and Debugging Designs with System Console............................................... 17 2.1. Introduction to System Console............................................................................. 17 2.2. System Console Debugging Flow............................................................................18 2.3. IP Cores that Interact with System Console............................................................. 19 2.3.1. Services Provided through Debug Agents.................................................... 19 2.4. Starting System Console.......................................................................................20 2.4.1. Starting System Console from Nios II Command Shell...................................20 2.4.2. Starting Stand-Alone System Console......................................................... 20 2.4.3. Starting System Console from Platform Designer (Standard)..........................20 2.4.4. Starting System Console from Intel Quartus Prime....................................... 21 2.4.5. Customizing Startup.................................................................................21 2.5. System Console GUI.............................................................................................21 2.5.1. System Explorer Pane...............................................................................22 2.6. System Console Commands.................................................................................. 23 2.7. Running System Console in Command-Line Mode.....................................................25 2.8. System Console Services...................................................................................... 26 2.8.1. Locating Available Services........................................................................26 2.8.2. Opening and Closing Services.................................................................... 27 2.8.3. SLD Service............................................................................................ 27 2.8.4. In-System Sources and Probes Service....................................................... 28 2.8.5. Monitor Service....................................................................................... 30 2.8.6. Device Service.........................................................................................32 2.8.7. Design Service........................................................................................ 33 2.8.8. Bytestream Service.................................................................................. 34 2.8.9. JTAG Debug Service................................................................................. 35 2.9. Working with Toolkits........................................................................................... 36 2.9.1. Convert your Dashboard Scripts to Toolkit API............................................. 36 2.9.2. Creating a Toolkit Description File...............................................................36 2.9.3. Registering a Toolkit................................................................................. 37 2.9.4. Launching a Toolkit.................................................................................. 37 Intel Quartus Prime Standard Edition User Guide: Debug Tools Send Feedback 2 Contents 2.9.5. Matching Toolkits with IP Cores..................................................................38 2.9.6. Toolkit API.............................................................................................. 38 2.10. ADC Toolkit....................................................................................................... 75 2.10.1. ADC Toolkit Terms.................................................................................. 78 2.10.2. Setting the Frequency of the Reference Signal............................................78 2.10.3. Tuning the Signal Generator.................................................................... 79 2.10.4. Running a Signal Quality Test...................................................................80 2.10.5. Running a Linearity Test..........................................................................81 2.10.6. ADC Toolkit Data Views........................................................................... 82 2.11. System Console Examples and Tutorials................................................................ 84 2.11.1. Nios II Processor Example....................................................................... 84 2.12. On-Board Intel FPGA Download Cable II Support.................................................... 86 2.13. MATLAB and Simulink* in a System Verification Flow ..............................................86 2.13.1. Supported MATLAB API Commands...........................................................88 2.13.2. High Level Flow......................................................................................88 2.14. Deprecated Commands.......................................................................................88 2.15. Analyzing and Debugging Designs with the System Console Revision History..............89 3. Debugging Transceiver Links........................................................................................ 91 3.1. Channel Manager.................................................................................................91 3.1.1. Channel Display Modes............................................................................. 93 3.2. Transceiver Debugging Flow Walkthrough................................................................93 3.3. Modifying the Design to Enable Transceiver Debug................................................... 93 3.3.1. Adapting an Intel FPGA Design Example .....................................................93 3.3.2. Stratix V Debug System Configuration........................................................ 96 3.3.3. Instantiating and Parameterizing Intel Arria 10 Debug IP cores.....................102 3.4. Programming the Design into an Intel FPGA...........................................................104 3.5. Loading the Design in the Transceiver Toolkit......................................................... 105 3.6. Linking Hardware Resources................................................................................ 105 3.6.1. Linking One Design to One Device............................................................ 107 3.6.2. Linking Two Designs to Two Devices..........................................................107 3.6.3. Linking One Design on Two Devices.......................................................... 107 3.6.4. Linking Designs and Devices on Separate Boards........................................108 3.6.5. Verifying Hardware Connections............................................................... 108 3.7. Identifying Transceiver Channels.......................................................................... 109 3.7.1. Controlling Transceiver Channels.............................................................. 109 3.8. Creating Transceiver Links...................................................................................109 3.9. Running Link Tests............................................................................................. 109 3.9.1. Running BER Tests................................................................................. 110 3.9.2. Signal Eye Margin Testing (Stratix V only)................................................. 110 3.9.3. Running Custom