Digital IC Design Methodology Felipe Prado Yonehara Digital IC Designer Decisions, Decisions • Take a CEO, a manager, and an individual contributor for a simple company. – The CEO’s “executive” decisions can have a great affect on the company, its partners, its products, and its customers. – The manager’s decision can have an affect on the managed team, and possibly other teams. – The individual contributor (IC) may have an affect on a specific project or task. CEO Manager Manager Manager Manager IC IC IC IC IC IC IC IC IC IC IC IC Decisions, Decisions (continued) • Just like the company organization, decisions made for IC design also have very different effects: – Decisions made at the specification level – Decisions made at the microarchitectural level – Decisions made at the RTL level Specification Micro Micro Micro Micro Architecture Architecture Architecture Architecture RTL RTL RTL RTL RTL RTL RTL RTL RTL RTL RTL RTL Objectives (of this module) • State the considerations in moving from specification to microarchitecture to RTL • State the considerations for selecting a process technology Topics for Digital IC Design Methodology • Day 1 – Specification – Microarchitecture – RTL coding – CMOS process selection • Day 2 – Implementation flow overview – Synthesis – Static timing analysis – Test – Floorplanning – Timing closure Topics in This Module • Specification • Microarchitecture • RTL coding • CMOS proccess selection Basic Flow: Implementation and Verification • flow Specification System Simulation Designer Micro-Architecture System Simulation Designer RTL Formal Verification Logic simulation Logic Syntesis Gates Synthesizable Gates Gate Level Simulation Place/Route Timing Placed/Route Gates Signoff Gates Verification Physical verification Place/Route Implementation GDSII What Is a Specification? • Ideas begin with a specification,which can be a textual, graphical, or even a software representation. Specification • Definition: A specification is an explicit set of requirements to be System Simulation Designer satisfied by a material, product, or service. • Example: The specification for the latest chip called for 250 MHz core clock with a 6G SERDES interface, able to process 1M streams of data per second at less than 10W total power Discussion • Who creates the specification? • What information is required to come up with the details of the specification? Specification Contents and Example Title Specification for XYZ Design List of Reviewers HW, SW, Test, Manufacturing, Customer, etc. Modification History 1.0 - 12/2007 – Initial Revision, 2.0 – 1/2008 – Changes to … Table of Contents Section 1 Overview - Section 2 Block 1 … Glossary XYZ = Codename for project, etc. Overview The XYZ chip is a new product targeted for consumers… Performance Targets 125 MHz, 1W Total Power, 1M streams/s Block Diagrams X Y Z Graphs Tables Pin D | Data Input | Data output Detailed Description Block A is input block, it receives signals ... Specification • For chip design, the specification is the reference model the team uses to: – Design the overall chip – Specify the intellectual property used – Specify the “new logic” to be created – Specify the block-level and chip-level interfaces – Partition the chip into functional blocks – Communicate interfaces and requirements with other teams – Measure actual performance versus specified targets Specification Snippet • Section 2.1 Block A Interface • Block A is the input which receives serial data from the I/O and transfers to Block B. din dout I/O Block A Block B Input clock (125 MHz) PORT NAME DIRECTION SOURCES/DESTINA SIZE DESCRIPTION NTION CLK INPUT I/O 1 bit Clock at 125 MHz Din Input I/O 32 bits Input data Dout Output A and B 32 bits Output data High-Level Decisions In creating or modifying the specification, high-level decisions that effect the system and its environment are made. • For example, the choice between external SRAM or DRAM: • Control for each one is drastically different • I/Os for the chip will be affected • Board itself will be affected, components plus signal routing • Another example is the choice to run the design at 125 MHz or 250 MHz • Chip-level clock input has to change • Software might have to change because the performance could be 2X different Discussion • What other decisions would be considered specification level? • How would we validate these decisions? Topics in this Module • Specification Microarchitecture • RTL coding • CMOS process selection Basic Flow: Implementation and Verification Specification System Simulation Designer Micro-Architecture System Simulation Designer RTL Formal Verification Logic simulation Logic Syntesis Gates Synthesizable Gates Gate Level Simulation Place/Route Timing Placed/Route Gates Signoff Gates Verification Physical verification Place/Route Implementation GDSII What Is Microarchitecture? • Step between the specification and RTL, the microarchitecture defines how the block will be implemented. • Definition: The Specification microarchitecture implements the pecification and defines System Simulation Designer specific mechanisms and structures for achieving that Micro-Architecture implementation. System Simulation Designer • Example: For Block A, the designer created a microarchitecture and partitioned his block into several smaller modules. Discussion • Who creates the microarchitecture? • What information is required to come up with the details of the microarchitecture? Microarchitecture • The microarchitecture is typically based on a block in the specification. Specification Microarchitecture Block A SPEC Block A bus 2 bus 1 bus 3 bus 1 Block Block A1 A3 SPEC Block Block bus 2 Block B A2 A4 Microarchitecture (continued) For chip design, the micro-architecture is the reference model the designers uses to • Design the block • Specify the intellectual property used • Specify the “new logic” to be created • Specify the block-level interfaces • Partition the block into more functional blocks • Communicate interfaces and requirements with other block designers • Measure actual performance versus specified targets Microarchitecture Snippet • This is the input block for Block A. Its function is to process and slice the data into 16-bit segments, based on control signals from the FSM, and send it to block B2. Sync FIFO Slicer bus 1a bus 1 bus 1a bus 1 (reg array) Block A1 (Datapath) FSM (Grey coded) PORT NAME DIRECTION SOURCE/DESTINA SIZE DESCRIPTION TION clk input I/O 1 bit Clock at 125MHz bus1 input I/O and Sync FIFO 32 bits Input data bus1a output Slicer 16 bits Output data Mid-Level Decisions In creating or modifying the microarchitecture, mid-level decisions that affect the block itself are made. • For example, the choice between internal SRAM or register array • Interface to the outside environment is the same. • Performance of the block may vary slightly, but functionality is the same. • The choice to use multiple datapath versus a single datapath • Area is tradeoff versus performance. • As long as the performance targets are met, how the design is actually implemented is a microarchitectural decision. Discussion • What other decisions would be considered microarchitecture level? • How would we validate these decisions? Topics in this Module • Specification • Microarchitecture RTL coding • CMOS process selection Basic Flow: Implementation and Verification Specification System Simulation Designer Micro-Architecture System Simulation Designer RTL Formal Verification Logic simulation Logic Syntesis Gates Synthesizable Gates Gate Level Simulation Place/Route Timing Placed/Route Gates Signoff Gates Verification Physical verification Place/Route Implementation GDSII What Is RTL? RTL (register transfer level) • Definition: A way of describing the operation of digital circuit where the behavior is defined in RTL terms of the flow of Formal signals between registers Verification Logic simulation Logic and the operations Syntesis performed • Example: The translation of a system specification to RTL is a difficult and time-consuming task. Discussion • Who creates the RTL? • What information is required to come up with the details of the RTL? RTL • The RTL is typically based on a block in the microarchitecture. Microarchitecture Block A1 Block A module block_a1 (..); input clk; input [31:0] bus1; bus 1 Block Block output[15:0] busa1; A1 A3 sync_fifo u1 (...); slicer u2 (...); Block Block bus 2 A2 A4 fsm u3 (...); endmodule RTL (continued) • For chip design, the RTL is the reference model the designer uses to – Design the block for final implementation – Instantiate and connect intellectual property – Code the “new logic” – Create the block-level interfaces – Partition the block into sub-blocks – Verify the interfaces to other blocks – Run simulations to measure actual performance versus specified targets RTL Snippet Sync FIFO ta Slicer bus 1 (reg array) (Datapath) bus 1a tb tc FSM (Grey coded) Low-Level Decisions • In creating or modifying the RTL, low level decisions that effect the implementation of the block itself are made. – For example, the choice to use a particular coding style • Designer has previous knowledge of an optimal style for implementation or verification • Designer is more comfortable with a particular style – The choice to add pipeline stages versus forcing more logic into a single cycle • Cycle time is traded off for sequential area • As long as the performance targets are met, how the design is actually implemented is a microarchitectural decision • It is possible the latency of the top-level block is “flexible”