A Framework and Analysis of Modern Graphics Architectures for General Purpose Programming Chris Thompson Sahngyun Hahn University of Washington satisfiability, solved using a genetic algorithm approach. We then Abstract compare the speed of our graphics card implementations to CPU Modern graphics hardware has become so powerful that raw implementations. In some cases, the results are startlingly performance enhancements are increasingly unnecessary. As such, impressive, yet there is also significant room for improvement. We recent graphics hardware architectures have begun to de-emphasize analyze the bottlenecks and propose minor architectural extensions performance enhancements in favor of versatility, offering rich to current graphics architectures which would improve their ways of programmatically reconfiguring the graphics pipeline. A effectiveness and efficiency for solving general purpose problems. side effect of this versatility is that new, powerful general purpose We conclude with a discussion of avenues for future work, constructs similar to vector processors are appearing in commodity including some which draw inspiration from earlier research in hardware. In this paper, we explore whether current graphics VLIW processors. architectures could be used to accelerate domains where vector processors would traditionally be used. We develop a programming 2 Prior work framework that allows us to solve computational problems using graphics hardware, and we apply it to various problems. We While the last decade was dominated by fixed function non- compare the speed of our graphics card implementations to programmable graphics architectures, some programmable graphics standard CPU implementations and demonstrate startling architectures were also explored. Some early systems, such as performance improvements in some cases, as well as room for Pixar’s CHAP [7] and the commercially available Ikonas platform improvement in others. We analyze the bottlenecks and propose [2], had user microcodable SIMD processors that could process minor architectural extensions to current graphics architectures vertex and pixel data in parallel. Programmable MIMD machines which would improve their effectiveness for solving general that could process triangles in parallel, such as the Pixel-Planes [3] purpose problems. and the SGI InfiniteReality, became popular for a short time, but their low-level custom microcodes were complex and rarely used by commercial developers. 1Introduction As transistor costs decreased, CPU vendors began to introduce Modern graphics hardware has reached a turning point where graphics-oriented SIMD processor extensions into general purpose performance enhancements are becoming less and less necessary. CPU designs. Examples of these extensions include Intel’s As McCool observes, performance levels of “cheap” video-game MMX/SSE instructions, AMD’s 3DNow architecture, and hardware are sufficient to overwrite every single pixel of a 640x480 Motorola’s AltiVec technology. While such extensions can display with its own transformed, lit, and textured polygon more accelerate a variety of graphics operations, they fall far short of the than 50 times every 30th of a second [9]. As such, recent graphics functionality of even a basic graphics chipset; for instance, none hardware—in both research and commercial designs—has begun to offer high level support for a rendering pipeline. For this reason, it de-emphasize performance enhancements in favor of versatility, is likely that all modern computer architectures for the foreseeable offering rich ways of programmatically reconfiguring the graphics future will include sophisticated graphics coprocessors, motivating pipeline [[8], [9], [13]]. A side effect of this versatility is that new, the work in this paper. Following industry conventions, we refer to powerful general purpose constructs similar to vector processors graphics coprocessors as GPUs [Graphics Processing Units]. are appearing in commodity PC hardware, thanks to their graphics chips. The power of these “graphics” processors should not be More recently, Sony developed a custom dual-processor SIMD underestimated; for example, the NVIDIA GeForce3 chip contains architecture for graphics called the Emotion Engine [5]. This design more transistors than the Intel Pentium IV, and its successor the is fully programmable. The first of the two processors is interfaced GeForce4 can perform more than 1.2 trillion operations per second. to the main CPU as a coprocessor, running instructions from the Most of the time, however, this power is going unused because it is application’s instruction stream, much like MMX or AltiVec. The only being exploited by graphics applications. second processor executes custom assembly subroutines for graphics or sound [8]. While the Emotion Engine is powerful, its We believe that current graphics architectures, with minor extremely high level of programmability has also earned it a evolutionary changes, could be used to accelerate other domains reputation for being difficult to program, since application writers where vector processors might traditionally be used. We believe must pay careful attention to very low-level details such as pipeline that this approach is important because, due to economic and other latency, hazards, and stalls throughout the rendering process. factors, it is unlikely that dedicated vector processors will ever become commonplace on the desktop, whereas powerful graphics Most new graphics architectures strike a balance between chips are already widely available. In this research, we investigate programmability and manageability by exposing only part of the the programming, performance, and limitations of a recent graphics rendering process to programmers. NVIDIA’s GeForce3 and ATI’s architecture on a pair of non-graphics problems, and we propose Radeon grant full programmatic control over the process through ways in which future iterations of the architecture could be which individual vertices are transformed from modeling space to improved to make it more suitable for such applications. world space. All attributes (position, color, normal vector, etc.) of each vertex may be programmatically altered via vertex programs We begin by describing a programming framework we have written in a custom assembly language. Later in the rendering devised that allows us to conveniently solve computational process, as new pixels are composited with old pixels on the screen, problems using graphics hardware. Our system includes a simulator the compositing process can be fully controlled through assembly for the graphics interface that can run on computers without special language pixel programs. Each programming model is designed to hardware. We implement a number of toy algorithms with our limit implementation complexity. For instance, every assembly framework, and we also apply the framework to a real problem: 3- 1 instruction has the same latency, memory accesses are only allowed Generate geometry to registers and the maximum number of different registers Transform geometry accessed by each instruction is capped so that the register files only Vertex programs need a small number of ports, and precisely one instruction is Clip to viewport issued per clock. None of these programming models was designed with general purpose non-graphics programming in mind, but as we Perform lighting demonstrate in this paper, they have the potential to evolve in this Rasterize geometry direction. Apply textures Pixel programs The work of Proudfoot et. al. [14] is closest in spirit to our own. In that work, the authors describe a language for developing Draw pixels arbitrarily complicated graphical shaders and a compiler for that language that generates code targeted to modern graphics Figure 2 A programmable graphics pipeline. architectures. The authors propose an innovative abstraction called The transform and lighting steps collapse together into one step in computation frequencies that allows them to combine vertex which the position, color, and lighting of geometry are determined programs and pixel programs under one high-level umbrella, and by vertex programs written in a custom assembly language. their compiler is intelligent enough to virtualize hardware resources Similarly, the texturing and pixel compositing stages are collapsed that may not exist on a given hardware target. However, because into a single stage where the output pixels are determined by pixel their work is oriented towards graphical shaders, it does not offer programs written in assembly language. any support for branches, labels, or main memory access, making it unsuitable for the kind of general purpose programming explored in For the remainder of this paper, we concentrate on a specific target, this paper. the NVIDIA GeForce4 chipset [[8], [12]]. This chipset is representative of modern graphics architectures. Its programming 3 Vertex and Pixel Programs interface is identical to the interface for NVIDIA’s earlier GeForce3 chipset, as well as for the chipset in Microsoft’s Xbox game console. It conforms fully to the DirectX 8 interface and can also be 3.1 The Graphics Pipeline accessed using a more basic application programming interface Traditionally, graphics hardware follows a fixed series of steps called OpenGL. called the graphics pipeline to render an image. These steps are illustrated below: 3.2 Vertex Programs Generate geometry In this section, we describe the GeForce3’s instruction set architecture for vertex programming.