TMS320C6452 DSP Peripheral Component Interconnect (PCI) User's Guide Literature Number: SPRUF86 October 2007 2 SPRUF86–October 2007 Submit Documentation Feedback Contents Preface ............................................................................................................................... 8 1 Introduction .............................................................................................................. 11 1.1 Purpose of the Peripheral ..................................................................................... 11 1.2 Features ......................................................................................................... 11 1.3 Features Not Supported ....................................................................................... 12 1.4 Functional Block Diagram ..................................................................................... 12 1.5 Supported Use Case Statement.............................................................................. 13 1.6 Industry Standard(s) Compliance Statement ............................................................... 13 2 Architecture.............................................................................................................. 14 2.1 Clock Control.................................................................................................... 14 2.2 Memory Map .................................................................................................... 14 2.3 Signal Descriptions ............................................................................................. 14 2.4 Pin Multiplexing ................................................................................................. 15 2.5 Byte Addressing ................................................................................................ 15 2.6 PCI Error Detection............................................................................................. 15 2.7 Status Reporting ................................................................................................ 17 2.8 Reset Considerations .......................................................................................... 17 2.9 Interrupt Support................................................................................................ 19 2.10 DMA Event Support ............................................................................................ 20 2.11 Emulation Considerations ..................................................................................... 20 2.12 PCI Configuration............................................................................................... 20 2.13 Connecting a Local PCI to an External PCI Device........................................................ 24 3 PCI Slave Operation................................................................................................... 26 3.1 Slave Memory Map............................................................................................. 26 3.2 Configuring Slave Window Registers ........................................................................ 26 3.3 Slave Access Address Translations.......................................................................... 28 3.4 Slave Configuration Operations .............................................................................. 29 3.5 Slave Memory Operations..................................................................................... 30 4 PCI Master Operation................................................................................................. 33 4.1 Master Memory Map ........................................................................................... 33 4.2 Configuring Master Windows ................................................................................. 34 4.3 Master Address Translation ................................................................................... 35 4.4 Master Configuration Operations ............................................................................. 36 4.5 Master I/O Operations ......................................................................................... 37 4.6 Master Memory Operations ................................................................................... 38 5 PCI Registers............................................................................................................ 39 5.1 PCI Configuration Registers................................................................................... 39 5.2 PCI Memory-Mapped Registers .............................................................................. 51 5.3 PCI Configuration Hook Registers ........................................................................... 79 SPRUF86–October 2007 Table of Contents 3 Submit Documentation Feedback List of Figures 1 PCI Block Diagram ......................................................................................................... 12 2 PCI Signals.................................................................................................................. 14 3 Internal and External Reset Inputs of the PCI Module ................................................................ 18 4 Signal Connections for I2C EEPROM Boot Mode ..................................................................... 23 5 PCI to External PCI Device ............................................................................................... 24 6 Slave Window Configuration.............................................................................................. 27 7 PCI-to-DSP Address Translation......................................................................................... 29 8 Master Window Configuration ............................................................................................ 34 9 PCI Address Substitution Register (0 to 31)............................................................................ 34 10 DSP-to-PCI Address Translation......................................................................................... 35 11 Example of DSP-to-PCI Address Translation .......................................................................... 35 12 Vendor Identification Register ............................................................................................ 40 13 Device Identification Register............................................................................................. 40 14 PCI Command Register ................................................................................................... 41 15 PCI Status Register ........................................................................................................ 42 16 Revision Identification Register........................................................................................... 43 17 Class Code Register ....................................................................................................... 43 18 Cache Line Size Register ................................................................................................. 44 19 Latency Timer Register.................................................................................................... 44 20 Header Type Register ..................................................................................................... 45 21 Built-In Self-Test Register ................................................................................................. 45 22 Base Address 0 Register.................................................................................................. 46 23 Base Address 1 Register.................................................................................................. 46 24 Base Address 2 Register.................................................................................................. 46 25 Base Address 3 Register.................................................................................................. 46 26 Base Address 4 Register.................................................................................................. 47 27 Base Address 5 Register.................................................................................................. 47 28 Subsystem Identification Register........................................................................................ 48 29 Subsystem Vendor Identification Register .............................................................................. 48 30 Capabilities Pointer Register.............................................................................................. 48 31 Interrupt Line Register ..................................................................................................... 49 32 Interrupt Pin Register ...................................................................................................... 49 33 Minimum Grant Register .................................................................................................. 50 34 Maximum Latency Register ............................................................................................... 50 35 Status Set and Status Clear Registers (PCISTATSET/PCISTATCLR) ............................................. 54 36 Host Interrupt Enable Set and Clear Registers (PCIHINTSET/PCIHINTCLR) ..................................... 58 37 DSP Interrupt Enable Set and Clear Registers (PCIDINTSET/PCIDINTCLR) ....................................