
Announcements • Upcoming deadlines Lecture 8 – HW2 due today – PA1 due on Thursday 2/8 Simple & Pipelined Processor Designs • Quiz 1 review session on Friday • Quiz 1 Christos Kozyrakis – Tue 2/6, 7pm–9pm, location TBD Stanford University – Local SCPD students must come to Stanford for the midterm http://eeclass.stanford.edu/ee108b – Covers lectures 1-7 – Closed book, 1 page of notes + green card, calculator C. Kozyrakis EE108b Lecture 8 1 C. Kozyrakis EE108b Lecture 8 2 Review: How to Execute Instructions Review: Datapath for Instruction Fetch Unit • First we need to: – Fetch the instruction • Then we need to: – Decode instruction / fetch register operands • Then we need to: – Do the operation Add 4 • Then we need to: – Write the result into register-file • Finally we need to: Read – Calculate the next instruction address PC address Instruction [31– 0] Instruction memory C. Kozyrakis EE108b Lecture 8 3 C. Kozyrakis EE108b Lecture 8 4 Review: Datapath for Arithmetic & Logical Review: Load Datapath Instructions • Extend datapath to support other immediate operations RegWrite • Extender handles either sign or zero extension ALUOp Instruction [25– 21] Read register 1 Read • MUX selects between ALU result and Memory output data 1 Instruction [20– 16] Read ALUSrc Zero Instruction register 2 0 Registers ALU [31– 0] Read 0 ALU M Write data 2 result u register M u Instruction [15– 11] x 1 Write x data 1 RegDst RegWrite 16 32 Instruction [15– 0] Sign ALUOp or Zero Instruction [25– 21] Read MemWrite extend register 1 Read Instruction [20– 16] Read data 1 ALUSrc MemtoReg Zero Instruction register 2 0 Registers ALU [31– 0] Read 0 ALU M Write data 2 result Address Read 1 register M data u M x u Instruction [15– 11] Write x u 1 Data x data 1 memory 0 Write RegDst data 16 32 Instruction [15– 0] Sign extend MemRead C. Kozyrakis EE108b Lecture 8 5 C. Kozyrakis EE108b Lecture 8 6 Review: Store Datapath Putting it All Together • Read Register 2 is passed on to Memory PC [31– 28] Instruction [25– 0] 00 0 1 M M u u • Memory address calculated just as in lw case x x Add ALU 1 0 result Add Shift left 2 Jump 4 Branch RegWrite ALUOp RegWrite Instruction [25– 21] Read MemWrite register 1 ALUOp Read Instruction [25– 21] MemWrite data 1 Read Instruction [20– 16] Read ALUSrc MemtoReg Read register 1 Zero PC address Read Instruction register 2 0 Registers ALU Instruction [20– 16] Read data 1 ALUSrc MemtoReg [31– 0] Read 0 ALU M Write data 2 result Address Read 1 register 2 Eq data InstructionInstruction u register M 0 Registers Read ALU ALU u M [31–[31– 0] 0] 0 Read x u M Write data 2 result Address 1 Instruction [15– 11] Write x Instruction register M data 1 Data x u M data 1 memory x u memory 0 Instruction [15– 11] Write x u Write 1 Data x data data 1 RegDst memory 0 Write 16 32 Instruction [15– 0] Sign RegDst data extend MemRead 16 32 Instruction [15– 0] Sign extend MemRead C. Kozyrakis EE108b Lecture 8 7 C. Kozyrakis EE108b Lecture 8 8 Control At Beginning Of Clock Cycle • Since every instruction takes one cycle, control is state free! PC [31– 28] Instruction [25– 0] 00 0 1 M M u u – It is just decoded instruction bits x x Add ALU 1 0 result Add Shift left 2 Jump • There are also few control points 4 <prev> Branch – Control on the multiplexers <prev> <prev> – Operation type for the ALU RegWrite <prev> ALUOp <prev> Instruction [25– 21] Read MemWrite – Write control on the Instruction & Data memories Read register 1 <prev> PC address Read <prev> Instruction [20– 16] Read data 1 ALUSrc MemtoReg Zero InstructionInstruction register 2 0 Registers ALU [31–[31– 0] 0] Read 0 ALU M Write data 2 result Address Read 1 Instruction register M data u M memory x u • First part of cycle does not have any control Instruction [15– 11] Write x u 1 Data x data 1 memory 0 Write – Which is good, since we don’t have instruction yet RegDst data <prev> 16 32 Instruction [15– 0] Sign extend MemRead <prev> • Look at setting of the control points for different instructions <prev> C. Kozyrakis EE108b Lecture 8 9 C. Kozyrakis EE108b Lecture 8 10 Control for Arithmetic Instruction Fetch at End PC [31– 28] Instruction [25– 0] 00 0 1 PC [31– 28] Instruction [25– 0] 00 0 1 M M M M u u u u x x x x Add ALU 1 0 Add ALU 1 0 result result Add Add Shift Shift left 2 Jump left 2 Jump 4 0 4 0 Branch Branch 0 0 X 1 1 RegWrite <op> RegWrite <op> ALUOp 0 ALUOp 0 Instruction [25– 21] Read MemWrite Instruction [25– 21] Read MemWrite Read register 1 0 Read register 1 0 PC address Read 0 PC address Read 0 Instruction [20– 16] Read data 1 ALUSrc MemtoReg Instruction [20– 16] Read data 1 ALUSrc MemtoReg Zero Zero InstructionInstruction register 2 InstructionInstruction register 2 0 Registers ALU 0 Registers ALU [31–[31– 0] 0] Read 0 ALU [31–[31– 0] 0] Read 0 ALU M Write data 2 result Address Read 1 M Write data 2 result Address Read 1 Instruction register M data Instruction register M data u M u M memory x u memory x u Instruction [15– 11] Write x u Instruction [15– 11] Write x u 1 Data x 1 Data x data 1 data 1 memory 0 memory 0 Write Write RegDst data RegDst data 1 16 32 1 16 32 Instruction [15– 0] Sign Instruction [15– 0] Sign extend MemRead extend MemRead X 0 X 0 C. Kozyrakis EE108b Lecture 8 11 C. Kozyrakis EE108b Lecture 8 12 Arithmetic Immediate ( ori ) Control for Load PC [31– 28] Instruction [25– 0] 00 0 1 PC [31– 28] Instruction [25– 0] 00 0 1 M M M M u u u u x x x x Add ALU 1 0 Add ALU 1 0 result result Add Add Shift Shift left 2 Jump left 2 Jump 4 0 4 0 Branch Branch 0 0 1 1 RegWrite Or RegWrite Add ALUOp 0 ALUOp 0 Instruction [25– 21] Read MemWrite Instruction [25– 21] Read MemWrite Read register 1 1 Read register 1 1 PC address Read 0 PC address Read 1 Instruction [20– 16] Read data 1 ALUSrc MemtoReg Instruction [20– 16] Read data 1 ALUSrc MemtoReg Zero Zero InstructionInstruction register 2 InstructionInstruction register 2 0 Registers ALU 0 Registers ALU [31–[31– 0] 0] Read 0 ALU [31–[31– 0] 0] Read 0 ALU M Write data 2 result Address Read 1 M Write data 2 result Address Read 1 Instruction register M data Instruction register M data u M u M memory x u memory x u Instruction [15– 11] Write x u Instruction [15– 11] Write x u 1 Data x 1 Data x data 1 data 1 memory 0 memory 0 Write Write RegDst data RegDst data 0 16 32 0 16 32 Instruction [15– 0] Sign Instruction [15– 0] Sign extend MemRead extend MemRead 0 0 1 1 C. Kozyrakis EE108b Lecture 8 13 C. Kozyrakis EE108b Lecture 8 14 Control for Store Control for Branch ( beq ) PC [31– 28] Instruction [25– 0] 00 0 1 PC [31– 28] Instruction [25– 0] 00 0 1 M M M M u u u u x x x x Add ALU 1 0 Add ALU 1 0 result result Add Add Shift Shift left 2 Jump left 2 Jump 4 0 4 0 Branch Branch 1 0 1 0 0 RegWrite Add RegWrite Sub ALUOp 1 ALUOp 0 Instruction [25– 21] Read MemWrite Instruction [25– 21] Read MemWrite Read register 1 1 Read register 1 0 PC address Read X PC address Read X Instruction [20– 16] Read data 1 ALUSrc MemtoReg Instruction [20– 16] Read data 1 ALUSrc MemtoReg Zero Zero InstructionInstruction register 2 InstructionInstruction register 2 0 Registers ALU 0 Registers ALU [31–[31– 0] 0] Read 0 ALU [31–[31– 0] 0] Read 0 ALU M Write data 2 result Address Read 1 M Write data 2 result Address Read 1 Instruction register M data Instruction register M data u M u M memory x u memory x u Instruction [15– 11] Write x u Instruction [15– 11] Write x u 1 Data x 1 Data x data 1 data 1 memory 0 memory 0 Write Write RegDst data RegDst data X 16 32 X 16 32 Instruction [15– 0] Sign Instruction [15– 0] Sign extend MemRead extend MemRead 1 0 X 0 C. Kozyrakis EE108b Lecture 8 15 C. Kozyrakis EE108b Lecture 8 16 Control for Jump ( j) Summary of Control Signals PC [31– 28] Instruction [25– 0] 00 0 1 M M u u x x func 10 0000 10 0010 Not Important Add ALU 1 0 result Add op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010 Shift left 2 Jump 4 1 add sub ori lw sw beq jump Branch 0 RegDst 1 1 0 0 x x x ALUSrc 0 0 1 1 1 0 x 0 RegWrite X MemtoReg 0 0 0 1 x x x ALUOp 0 Instruction [25– 21] Read MemWrite Read register 1 X PC address Read X RegWrite 1 1 1 1 0 0 0 Instruction [20– 16] Read data 1 ALUSrc MemtoReg Zero InstructionInstruction register 2 0 Registers ALU MemWrite 0 0 0 0 1 0 0 [31–[31– 0] 0] Read 0 ALU M Write data 2 result Address Read 1 Instruction register M data u M memory x u Branch 0 0 0 0 0 1 0 Instruction [15– 11] Write x u 1 Data x data 1 memory 0 Write Jump 0 0 0 0 0 0 1 RegDst data X 16 32 Instruction [15– 0] Sign ExtOp x x 0 1 1 x x extend MemRead X 0 ALUctr<2:0> Add Sub Or Add Add Sub xxx C.
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