Intel® Itanium® Architecture Software Developer’s Manual Volume 4: IA-32 Instruction Set Reference Revision 2.3 May 2010 Document Number: 323208 THIS DOCUMENT IS PROVIDED “AS IS” WITH NO WARRANTIES WHATSOEVER, INCLUDING ANY WARRANTY OF MERCHANTABILITY, FITNESS FOR ANY PARTICULAR PURPOSE, OR ANY WARRANTY OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE. Information in this document is provided in connection with Intel® products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. 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Intel® Itanium® Architecture Software Developer’s Manual, Rev. 2.3 398 Contents 1 About this Manual . 4:1 1.1 Overview of Volume 1: Application Architecture . 4:1 1.1.1 Part 1: Application Architecture Guide . 4:1 1.1.2 Part 2: Optimization Guide for the Intel® Itanium® Architecture . 4:1 1.2 Overview of Volume 2: System Architecture. 4:2 1.2.1 Part 1: System Architecture Guide . 4:2 1.2.2 Part 2: System Programmer’s Guide . 4:3 1.2.3 Appendices. 4:4 1.3 Overview of Volume 3: Intel® Itanium® Instruction Set Reference . 4:4 1.4 Overview of Volume 4: IA-32 Instruction Set Reference. 4:4 1.5 Terminology . 4:5 1.6 Related Documents . 4:5 1.7 Revision History . 4:6 2 Base IA-32 Instruction Reference . 4:11 2.1 Additional Intel® Itanium® Faults . 4:11 2.2 Interpreting the IA-32 Instruction Reference Pages . 4:12 2.2.1 IA-32 Instruction Format . 4:12 2.2.2 Operation . 4:15 2.2.3 Flags Affected. 4:18 2.2.4 FPU Flags Affected . 4:18 2.2.5 Protected Mode Exceptions . 4:19 2.2.6 Real-address Mode Exceptions . 4:19 2.2.7 Virtual-8086 Mode Exceptions . 4:19 2.2.8 Floating-point Exceptions . 4:20 2.3 IA-32 Base Instruction Reference. 4:20 3IA-32 Intel® MMX™ Technology Instruction Reference . 4:399 4 IA-32 SSE Instruction Reference . 4:463 4.1 IA-32 SSE Instructions . 4:463 4.2 About the Intel® SSE Architecture . 4:463 4.3 Single Instruction Multiple Data . 4:464 4.4 New Data Types . 4:464 4.5 SSE Registers . 4:465 4.6 Extended Instruction Set. 4:465 4.6.1 Instruction Group Review . 4:466 4.7 IEEE Compliance . 4:474 4.7.1 Real Number System . 4:474 4.7.2 Operating on NaNs. 4:480 4.8 Data Formats . 4:481 4.8.1 Memory Data Formats . 4:481 4.8.2 SSE Register Data Formats . 4:481 4.9 Instruction Formats . 4:483 4.10 Instruction Prefixes . 4:483 4.11 Reserved Behavior and Software Compatibility . 4:484 4.12 Notations. 4:484 4.13 SIMD Integer Instruction Set Extensions . 4:562 4.14 Cacheability Control Instructions . 4:575 Index . 4:583 Intel® Itanium® Architecture Software Developer’s Manual, Rev. 2.3 399 Figures 2-2 Bit Offset for BIT[EAX,21]. 4:18 2-3 Memory Bit Indexing. 4:18 2-4 Version Information in Registers EAX . 4:79 3-1 Operation of the MOVD Instruction . 4:401 3-2 Operation of the MOVQ Instruction . 4:403 3-3 Operation of the PACKSSDW Instruction. 4:405 3-4 Operation of the PACKUSWB Instruction. 4:408 3-5 Operation of the PADDW Instruction . 4:410 3-6 Operation of the PADDSW Instruction . 4:413 3-7 Operation of the PADDUSB Instruction . 4:416 3-8 Operation of the PAND Instruction . 4:419 3-9 Operation of the PANDN Instruction. 4:421 3-10 Operation of the PCMPEQW Instruction . 4:423 3-11 Operation of the PCMPGTW Instruction . 4:426 3-12 Operation of the PMADDWD Instruction . 4:429 3-13 Operation of the PMULHW Instruction . 4:431 3-14 Operation of the PMULLW Instruction . 4:433 3-15 Operation of the POR Instruction. 4:435 3-16 Operation of the PSLLW Instruction . 4:437 3-17 Operation of the PSRAW Instruction . 4:440 3-18 Operation of the PSRLW Instruction . 4:443 3-19 Operation of the PSUBW Instruction . 4:446 3-20 Operation of the PSUBSW Instruction . ..