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Xilinx/Cadence PCB Guide www.xilinx.com R Preface About This Guide This guide contains information for FPGA designers and Printed Circuit Board (PCB) engineers about processes and mechanisms available within ISE and various Cadence tools to efficiently implement an FPGA on a PCB. The first section of the guide covers the PCB and FPGA design flows highlighting steps in these flows where data is exchanged between these two software environments. Then for each identified step the guide details processes, files, and options available to perform the identified task. With Cadence’s broad software package availability, we cannot cover all of the features available to implement a printed circuit board with FPGAs in this document. For full details regarding these tools, please refer to Cadence’s documentation available at: www.cadence.com/support/sourcelink.aspx. If you use multiple vendor software tools for your PCB design flow, such as Cadence OrCAD for schematic capture with Mentor Graphics PADs for PCB layout, refer to the vendor specific documentation. For Mentor Graphics tools please refer to the “Xilinx/ Mentor Graphics PCB Guide” for additional information. For other PCB software packages, please refer to the specific documentation for those tools. Additional Resources To find additional documentation, see the Xilinx website at: http://www.xilinx.com/literature. To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support. To find additional documentation regarding Cadence PCB design tools, see: www.cadence.com/support/sourcelink.aspx. Xilinx/Cadence PCB Guide www.xilinx.com 3 Preface: About This Guide R 4 www.xilinx.com Xilinx/Cadence PCB Guide Table of Contents Preface: About This Guide Additional Resources . 3 Xilinx/Cadence PCB Guide Implementing a Xilinx FPGA on a Printed Circuit Board . 7 Design Flow . 7 Schematic Capture Tool in the FPGA Design Flow . 9 PCB Layout Tool in the FPGA Design Flow . 9 Cadence PCB Design Tools. 9 Cadence OrCAD Series. 10 Cadence Allegro Series . 10 Multi-Vendor Flow . 10 Common Tasks . 10 Create an Initial FPGA Pinout . 10 Necessary Information . 10 Process . 11 Generate an Initial FPGA I/O User Constraint File (UCF) . 12 UCF Creation with a Text Editor . 13 UCF Creation with PACE or Floorplan Editor . 13 UCF Creation with the PIN2UCF Utility . 13 Create a Schematic Symbol (Schematic Shape and Content) . 14 Necessary Information . 14 Process . 14 Create a Layout Symbol . 15 Map Schematic Symbols to the Layout Symbol . 16 Update ISE from Pinout Changes Done in the Schematic Tool . 16 Process . 16 Update ISE with Pinout Changes Done in the Layout Tool . 16 Process . 16 Update the PCB Database with Pinout Changes Done in ISE . 16 Process . 17 Xilinx/Cadence PCB Guide www.xilinx.com 5 R 6 www.xilinx.com Xilinx/Cadence PCB Guide R Xilinx/Cadence PCB Guide This guide contains the following sections: • “Implementing a Xilinx FPGA on a Printed Circuit Board” • “Common Tasks” Implementing a Xilinx FPGA on a Printed Circuit Board In recent years, the design of FPGAs and printed circuit boards (PCBs) have become increasingly parallelized as opposed to the traditional sequential model. This is mostly due to market pressure that demands a fast design cycle and rapid adaptability to specification changes. In the past the FPGA was typically designed before the board or was added to an already designed board to perform some glue logic function, voltage or protocol conversion. Often the same PCB engineers were doing both the FPGA and PCB designs. Today, with their increasing internal and I/O capabilities, FPGAs can take on more core features of an application which require longer development time and greater expertise and manpower. On the board side, tight form factor, signal integrity, and electromagnetic regulations require sharp skills and dedicated personnel. Therefore, FPGA and PCB are now two separate design teams working in different environments and often physically distant. Paradoxically, pressures in terms of time and adaptability to market requires many more interactions between these design environments so that functionality, performance and cost objective are delivered on time. In practice, this translates into back and forth data exchanges throughout the design process between design teams to update the board symbols or FPGA constraints. Design Flow Figure 1, page 8, System Development Cycle, shows a typical flow in the PCB and FPGA development cycle (white boxes). It also highlights the steps that require communication between FPGA and PCB software tools (grey boxes). “Common Tasks,” page 10 details the mechanisms and processes available to perform each of these data exchanges. Xilinx/Cadence PCB Guide www.xilinx.com 7 R System Architecture Specification FPGA Design Cycle PCB Design Cycle Design Exploration Design Exploration Constraints: Constraints: Placement Placement Timing Timing Routing Routing Power Signal integrity Power Create Initial FPGA Pinout 1. Generate Initial FPGA 2. Create Initial FPGA I/O Constraint File (UCF) Schematic Symbol 3. Create Layout Symbol Initial Implementation Initial Implementation Logic design Schematic capture Implementation Layout Verifications Verifications Update FPGA Pinout 4. Update FPGA 5. Update Schematic Symbol I/O Constraint File Y FPGA 6. Update Layout Symbol PCB Y Perf. Perf. met? met? N N Subsequent Implementation(s) Changes: Subsequent Implementation(s) I/O layout Due to changes in: Due to changes in: I/O properties Timing constraints Layout constraints Pin swapped Placement constraints Redesign connectivity Pin added Routing constraints I/O Layout Pin removed Logic redesign I/O properties Pin moved Implementation strategies NNFPGA N PCB N Perf. Perf. met? met? Y Y Syst NN Perf. met? Y Done X10509 Figure 1: System Design Cycle with FPGA and PCB Databases Synchronization Steps Highlighted 8 www.xilinx.com Xilinx/Cadence PCB Guide Implementing a Xilinx FPGA on a Printed Circuit Board R PCB design requires two main tools; a schematic capture tool and a layout tool. These tools are described in the following sections. Schematic Capture Tool in the FPGA Design Flow The schematic capture tool enables designers to create a graphical representation of connections between components on the PCB. This data helps anyone involved in the project to understand how components on this board are connected between themselves and with the outside world. The layout designer also uses this information to physically place and route all signals on the PCB. Tips: Since an FPGA is a programmable component, its requirements on the PCB are unique to your application. Xilinx recommends that you add within the schematic all the specific components necessary for both the programming and the behavior of this device in your particular application.