Vivado Design Suite User Guide Designing with IP UG896 (v2019.2) March 3, 2020 Revision History The following table shows the revision history for this document. Section Revision Summary 03/03/2020 2019.2 General Updates Editorial updates. Editing Subsystem IP in Appendix D Corrected the command for editing subsystem IP. 06/12/2019 2019.1 General Updates Editorial updates. Setting the IP Cache Updated information for cache names. 12/18/2018 2018.3 General Updates Editorial updates. Verification IP Added information for use of Verification IP (VIP) for interfaces. 06/06/2018 Version 2018.2 General Updates Editorial updates only. No technical content updates. 04/04/2018 Version 2018.1 General Updates Initial Xilinx release for 2018.1. Updated commands and screen examples. Updated Report > Status menu. Selectively Upgrading IP Added a section on selective upgrade on IP. Managing IP Settings Added a Caution in on managing IP settings. Managed IP Features Added an Important Note on use of AXI Peripherals. Tcl Commands for Common IP Operations Added new Tcl commands. Editing Subsystem IP in Appendix D Updated how to edit subsystem IP. Designing with IP Send Feedback 2 UG896 (v2019.2) March 3, 2020 www.xilinx.com Table of Contents Chapter 1: IP-Centric Design Flow Introduction . 5 IP Terminology . 7 IP Packager . 8 IP Integrator . 9 Using Revision and Source Control. 9 Using Encryption . 9 Chapter 2: IP Basics Introduction . 10 Using IP Project Settings . 11 Using the IP Catalog. 18 Creating an IP Customization . 25 Instantiating an IP . 34 Understanding IP States Within a Project . 37 Managing IP Constraints . 37 Setting the Target Clock Period. 41 Synthesis Options for IP. 45 Simulating IP. 47 Upgrading IP. 52 Understanding Multi-Level IP . 56 Working with Debug IP . 58 Using a Core Container . 60 Chapter 3: Using Manage IP Projects Introduction . 67 Managed IP Features . 68 Using the Manage IP Flow. 68 Chapter 4: Using IP Example Designs Introduction . 72 Opening an Example Design . 72 Examining Standalone IP . 74 Designing with IP Send Feedback 3 UG896 (v2019.2) March 3, 2020 www.xilinx.com Chapter 5: Using Xilinx IP with Third-Party Synthesis Tools Introduction . 75 Third-Party Synthesis Flow . 75 Chapter 6: Tcl Commands for Common IP Operations Introduction . 78 Using IP Tcl Commands In Design Flows. 78 Tcl Commands for Common IP Operations . 80 Example IP Flow Commands . 82 Appendix A: Determining Why IP is Locked Introduction . 87 Appendix B: IP Files and Directory Structure Introduction . 93 IP-Generated Directories and Files . 93 Files Associated with IP . 95 Using a COE File . 95 Appendix C: Using the Platform Board Flow for IP Introduction . 100 Appendix D: Editing or Overriding IP Sources Introduction . 106 Overriding IP Constraints. 106 Editing IP Sources. 109 Editing Subsystem IP . 110 Appendix E: Additional Resources and Legal Notices Xilinx Resources . 111 Solution Centers. 111 Documentation Navigator and Design Hubs . 111 References . 112 Please Read: Important Legal Notices . 114 Designing with IP Send Feedback 4 UG896 (v2019.2) March 3, 2020 www.xilinx.com Chapter 1 IP-Centric Design Flow Introduction The Xilinx® Vivado® Design Suite provides an intellectual property (IP) centric design flow that lets you add IP modules to your design from various design sources. Central to the environment is an extensible IP catalog that contains Xilinx-delivered Plug-and-Play IP. The IP catalog can be extended by adding the following: • Modules from System Generator for DSP designs (MATLAB® from Simulink® algorithms) • Vivado High-Level Synthesis (HLS) designs (C/C++ algorithms) •Third-party IP • Designs packaged as IP using the Vivado IP packager tool Figure 1-1 illustrates the IP-centric design flow. Designing with IP Send Feedback 5 UG896 (v2019.2) March 3, 2020 www.xilinx.com Chapter 1: IP-Centric Design Flow X-Ref Target - Figure 1-1 RTL IP Source Files Simulation VHDL, Verilog, Example Test Document Block Design Model Files SystemVerilog*, Designs Bench Files (BD) (simsets) (XCI/XCIX) *SystemVerilog files must have a Verilog Wrapper. RTL Source Files VHDL, Verilog, SystemVerilog*, IP Packager (XCI/XCIX) IP Catalog Xilinx IP Add Module 3rd Party IP User IP X14070-030917 Figure 1-1: IP-Centric Design Flow Note: In some cases, third-party providers offer IP as synthesized EDIF netlists. You can load these files into a Vivado design using the Add Sources command. The available methods to work with IP in a design are: • Use the Managed IP flow to customize IP and generate output products, including a synthesized design checkpoint (DCP) to preserve the customization for use in the current and future releases. See Chapter 3, Using Manage IP Projects for more information. Designing with IP Send Feedback 6 UG896 (v2019.2) March 3, 2020 www.xilinx.com Chapter 1: IP-Centric.