See all versions of this document Vivado Design Suite User Guide Implementation UG904 (v2021.1) August 30, 2021 Revision History Revision History The following table shows the revision history for this document. Section Revision Summary 08/30/2021 Version 2021.1 Sweep (Default) Added more information. Incremental Implementation Controls Corrected Block Memory and DSP placement example. Using Incremental Implementation in Project Mode Corrected steps and updated image. Using report_incremental_reuse Updated Reuse Summary example and Reference Run Comparison. Physical Optimization Reports Updated to clarify that report is not cumulative. Available Logic Optimizations Added -resynth_remap. Resynth Remap Added logic optimization. opt_design Added [-resynth_remap] to opt_design Syntax. Physical Synthesis Phase Added entry for Property-Based Retiming. 02/26/2021 Version 2020.2 General Updates General release updates. 08/25/2020 Version 2020.1 Appendix A: Using Remote Hosts and Compute Clusters Updated section. UG904 (v2021.1) August 30, 2021Send Feedback www.xilinx.com Implementation 2 Table of Contents Revision History...............................................................................................................2 Chapter 1: Preparing for Implementation....................................................... 5 About the Vivado Implementation Process............................................................................. 5 Navigating Content by Design Process.................................................................................... 8 Managing Implementation........................................................................................................ 8 Configuring, Implementing, and Verifying IP........................................................................14 Guiding Implementation with Design Constraints............................................................... 14 Using Checkpoints to Save and Restore Design Snapshots................................................ 17 Chapter 2: Implementing the Design................................................................18 Running Implementation in Non-Project Mode....................................................................18 Running Implementation in Project Mode............................................................................ 22 Customizing Implementation Strategies............................................................................... 33 Launching Implementation Runs............................................................................................39 Moving Processes to the Background.................................................................................... 41 Running Implementation in Steps.......................................................................................... 41 About Implementation Commands........................................................................................ 43 Implementation Sub-Processes.............................................................................................. 43 Opening the Synthesized Design............................................................................................ 45 Logic Optimization.................................................................................................................... 50 Power Optimization.................................................................................................................. 65 Placement...................................................................................................................................67 Physical Optimization............................................................................................................... 84 Routing..................................................................................................................................... 100 Incremental Implementation................................................................................................ 109 Chapter 3: Analyzing and Viewing Implementation Results............. 129 Monitoring the Implementation Run................................................................................... 129 Moving Forward After Implementation............................................................................... 132 Viewing Messages...................................................................................................................134 Viewing Implementation Reports......................................................................................... 137 UG904 (v2021.1) August 30, 2021Send Feedback www.xilinx.com Implementation 3 Modifying Implementation Results...................................................................................... 141 Vivado ECO Flow......................................................................................................................168 Appendix A: Using Remote Hosts and Compute Clusters....................189 Overview...................................................................................................................................189 Requirements.......................................................................................................................... 189 Manual Configuration.............................................................................................................190 Cluster Configurations............................................................................................................192 Launching Jobs on Remote Hosts......................................................................................... 196 Appendix B: ISE Command Map..........................................................................198 Tcl Commands and Options...................................................................................................198 Appendix C: Implementation Categories, Strategy Descriptions, and Directive Mapping........................................................................................ 199 Implementation Categories...................................................................................................199 Implementation Strategy Descriptions................................................................................ 199 Directives Used by opt_design and place_design in Implementation Strategies........... 201 Directives Used by phys_opt_design and route_design in Implementation Strategies. 202 Appendix D: Additional Resources and Legal Notices........................... 205 Xilinx Resources.......................................................................................................................205 Documentation Navigator and Design Hubs...................................................................... 205 References................................................................................................................................205 Training Resources..................................................................................................................206 Please Read: Important Legal Notices................................................................................. 207 UG904 (v2021.1) August 30, 2021Send Feedback www.xilinx.com Implementation 4 Chapter 1: Preparing for Implementation Chapter 1 Preparing for Implementation About the Vivado Implementation Process The Xilinx® Vivado® Design Suite enables implementation of the following Xilinx device architectures: Versal™ adaptive compute acceleration platform (ACAP), UltraScale™, UltraScale+™, and Xilinx 7 series FPGA. A variety of design sources are supported, including: • RTL designs • Netlist designs • IP-centric design flows shows the Vivado tools flow. Vivado implementation includes all steps necessary to place and route the netlist onto device resources, within the logical, physical, and timing constraints of the design. For more information about the design flows supported by the Vivado tools, see the Vivado Design Suite User Guide: Design Flows Overview (UG892). SDC and XDC Constraint Support The Vivado Design Suite implementation is a timing-driven flow. It supports industry standard Synopsys Design Constraints (SDC) commands to specify design requirements and restrictions, as well as additional commands in the Xilinx Design Constraints format (XDC). UG904 (v2021.1) August 30, 2021Send Feedback www.xilinx.com Implementation 5 Chapter 1: Preparing for Implementation Figure 1: Vivado Design Suite High-Level Design Flow IP Integration High-Level DSP Design (System (Embedded, Logic, Custom IP C Sources Synthesis Generator) DSP…) IP Packaging IP Catalog Sources-RTL, Netlist, RTL System-Level Integration Xilinx IP Constraints Third-Party IP User IP Synthesis Design Analysis Constraints Implementation Simulation Debugging Cross Probing Programming ECO and Debug X12973-040716 Vivado Implementation Sub-Processes The Vivado Design Suite implementation process transforms a logical netlist and constraints into a placed and routed design, ready for bitstream generation. The implementation process walks through the following sub-processes: 1. Opt Design: Optimizes the logical design to make it easier to fit onto the target Xilinx device. 2. Power Opt Design (optional): Optimizes design elements to reduce the power demands of the target Xilinx device. 3. Place Design: Places the design onto the target Xilinx device and performs fanout replication to improve timing. 4. Post-Place Power