On-Chip Communication Architectures pprelims-p373892.inddrelims-p373892.indd i 33/18/2008/18/2008 22:25:41:25:41 PPMM The Morgan Kaufmann Series in Systems on Silicon Series Editor , Wayne Wolf, Georgia Institute of Technology The Designer ’ s Guide to VHDL, Second System-on-Chip Test Architectures Edition Edited by Laung-Terng Wang, Charles Stroud, Peter J. Ashenden and Nur Touba The System Designer ’ s Guide to Verifi cation Techniques for System- VHDL-AMS Level Design Peter J. Ashenden, Gregory D. Peterson, and Masahiro Fujita, Indradeep Ghosh, and Mukul Darrell A. Teegarden Prasad Modeling Embedded Systems and VHDL-2008: Just the New Stuff SoCs Peter J. Ashenden and Jim Lewis Axel Jantsch On-Chip Communication ASIC and FPGA Verifi cation: A Guide Architectures: System on Chip to Component Modeling Interconnect Richard Munden Sudeep Pasricha and Nikil Dutt Multiprocessor Systems-on-Chips Edited by Ahmed Amine Jerraya and Wayne To Come Wolf Embedded DSP Processor Design: Functional Verifi cation Application Specifi c Instruction Set Bruce Wile, John Goss, and Wolfgang Roesner Processors Dake Liu Customizable and Confi gurable Embedded Processors Processor Description Languages Edited by Paolo Ienne and Rainer Leupers Prabhat Mishra Networks-on-Chips: Technology and Tools Edited by Giovanni De Micheli and Luca Benini VLSI Test Principles & Architectures Edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen Designing SoCs with Confi gured Processors Steve Leibson ESL Design and Verifi cation Grant Martin, Andrew Piziali, and Brian Bailey Aspect-Oriented Programming with e David Robinson Reconfi gurable Computing: The Theory and Practice of FPGA-Based Computation Edited by Scott Hauck and André DeHon pprelims-p373892.inddrelims-p373892.indd iiii 33/18/2008/18/2008 22:25:41:25:41 PPMM On-Chip Communication Architectures System on Chip Interconnect Sudeep Pasricha – Nikil Dutt AMSTERDAM • BOSTON • HEIDELBERG • LONDON NEW YORK • OXFORD • PARIS • SAN DIEGO SAN FRANCISCO • SINGAPORE • SYDNEY • TOKYO Morgan Kaufmann is an imprint of Elsevier pprelims-p373892.inddrelims-p373892.indd iiiiii 33/18/2008/18/2008 22:25:41:25:41 PPMM Senior Acquisitions Editor: Charles B. Glaser Publishing Services Manager: George Morrison Project Manager: Mónica González de Mendoza Assistant Editor: Greg Chalson Cover Design: Dennis Schaefer Morgan Kaufmann Publishers is an imprint of Elsevier. 30 Corporate Drive, Suite 400, Burlington, MA 01803, USA This book is printed on acid-free paper. © 2008 Elsevier, Inc. All rights reserved. Designations used by companies to distinguish their products are often claimed as trademarks or registered trademarks. In all instances in which Morgan Kaufmann Publishers is aware of a claim, the product names appear in initial capital or all capital letters. Readers, however, should contact the appropriate companies for more complete information regarding trademarks and registration. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means – electronic, mechanical, photocopying, scanning, or otherwise – without prior written permission of the publisher. Permissions may be sought directly from Elsevier ’ s Science & Technology Rights Department in Oxford, UK: phone: (ϩ44) 1865 843830, fax: (ϩ44) 1865 853333, E-mail: [email protected]. You may also complete your request online via the Elsevier homepage (http://elsevier.com ), by selecting “ Support & Contact ” then “ Copyright and Permission ” and then “ Obtaining Permissions. ” Library of Congress Cataloging-in-Publication Data Pasricha, Sudeep.. On-chip communication architectures: system on chip interconnect/Sudeep Pasricha, Nikil Dutt. p. cm. Includes bibliographical references and index. ISBN-13: 978-0-12-373892-9 (hardback: alk. paper) 1. Systems on a chip. 2. Microcomputers—Buses 3. Computer architecture. 4. Interconnects (Integrated circuit technology) I. Dutt, Nikil. II. Title. TK7895.E42P4 2008 621.3815—dc22 2008004691 ISBN: 978-0-12-373892-9 For information on all Morgan Kaufmann publications, visit our Web site at www.mkp.com or www.books.elsevier.com 08 09 10 11 12 13 10 9 8 7 6 5 4 3 2 1 Printed in the United States of America pprelims-p373892.inddrelims-p373892.indd iivv 33/18/2008/18/2008 22:25:42:25:42 PPMM Contents Preface ix About the Authors xiii Acknowledgments xv List of Contributors xvii CHAPTER 1 Introduction ........................................................................................1 1.1 Trends in System-On-Chip Design .....................................................1 1.2 Coping with Soc Design Complexity ................................................ 3 1.3 ESL Design Flow ................................................................................4 1.4 On-Chip Communication Architectures: A Quick Look .....................6 1.5 Book Outline ...................................................................................12 CHAPTER 2 Basic Concepts of Bus-Based Communication Architectures .................................................................................... 17 2.1 Terminology ....................................................................................18 2.2 Characteristics of Bus-Based Communication Architectures ...........19 2.3 Data Transfer Modes ........................................................................28 2.4 Bus Topology Types ......................................................................... 33 2.5 Physical Implementation of Bus Wires ............................................ 37 2.6 Discussion: Buses in the DSM Era ....................................................38 2.7 Summary ..........................................................................................39 CHAPTER 3 On-Chip Communication Architecture Standards ............................... 43 3.1 Standard On-Chip Bus-Based Communication Architectures .......... 44 3.2 Socket-Based On-Chip Bus Interface Standards ...............................88 3.3 Discussion: Off-Chip Bus Architecture Standards ............................ 96 3.4 Summary ..........................................................................................97 CHAPTER 4 Models for Performance Exploration .............................................. 101 4.1 Static Performance Estimation Models ..........................................102 4.2 Dynamic (Simulation-Based) Performance Estimation Models ......111 4.3 Hybrid Communication Architecture Performance Estimation Approaches .................................................................................... 132 4.4 Summary ........................................................................................138 CHAPTER 5 Models for Power and Thermal Estimation ...................................... 143 5.1 Bus Wire Power Models .................................................................145 5.2 Comprehensive Bus Architecture Power Models .......................... 153 5.3 Bus Wire Thermal Models ..............................................................167 pprelims-p373892.inddrelims-p373892.indd v 33/18/2008/18/2008 22:25:42:25:42 PPMM vi Contents 5.4 Discussion: PVT Variation-Aware Power Estimation ....................174 5.5 Summary .....................................................................................179 CHAPTER 6 Synthesis of On-Chip Communication Architectures .............................................................................. 185 6.1 Bus Topology Synthesis ...............................................................187 6.2 Bus Protocol Parameter Synthesis ...............................................196 6.3 Bus Topology and Protocol Parameter Synthesis .........................205 6.4 Physical Implementation Aware Synthesis .................................. 216 6.5 Memory–Communication Architecture Co-synthesis ..................230 6.6 Discussion: Physical and Circuit Level Design of On-Chip Communication Architectures ....................................................240 6.7 Summary .....................................................................................243 CHAPTER 7 Encoding Techniques for On-Chip Communication Architectures ............................................................................... 253 7.1 Techniques for Power Reduction ................................................255 7.2 Techniques for Reducing Capacitive Crosstalk Delay .................278 7.3 Techniques for Reducing Power and Capacitive Crosstalk Effects ..........................................................................282 7.4 Techniques for Reducing Inductive Crosstalk Effects .................284 7.5 Techniques for Fault Tolerance and Reliability ............................287 7.6 Summary .....................................................................................292 CHAPTER 8 Custom Bus-Based On-Chip Communication Architecture Design .................................................................... 301 8.1 Split Bus Architectures ................................................................301 8.2 Serial Bus Architectures ..............................................................309 8.3 CDMA-Based Bus Architectures ................................................... 310 8.4 Asynchronous Bus Architectures ................................................313 8.5 Dynamically Reconfi gurable Bus Architectures .......................... 318 8.6 Summary .....................................................................................336