MASTER THESIS A DFT BASED SYNCHRONIZATION SCHEME FOR CHIRPED COMMUNICATION René Moll FACULTY OF ELECTRICAL ENGINEERING, MATHEMATICS AND COMPUTER SCIENCE COMPUTER ARCHITECTURE FOR EMBEDDED SYSTEMS EXAMINATION COMMITTEE Prof.dr.ir. G.J.M. Smit (CAES) Dr. ir A.B.J. Kokkeler (CAES) Dr.ir. R.A.R. van der Zee (ICD) R. Dutta, M.Sc (ICD/CAES/SRR) 04-02-2013 A DFT based synchronization scheme for chirped communication Master’s Thesis by René Moll S0214671 Committee: Prof.dr.ir. G.J.M. Smit (CAES) Dr. ir A.B.J. Kokkeler (CAES) Dr.ir. R.A.R. van der Zee (ICD) R. Dutta, M.Sc (ICD/CAES/SRR) University of Twente, Enschede, The Netherlands February 4, 2013 Abstract The goal of this thesis was to derive a synchronization algorithm for chirped wireless commu- nication systems and provide a high level implementation of this algorithm. The main require- ments were speed, accuracy and low power consumption. This work has been done to extend a chirped binary frequency shift-keying (BFSK) receiver developed at the Integrated Circuit Design, Computer Architectures and Embedded Systems and Short Range Radio chairs at the University of Twente. Based on chirp signal properties, an algorithm has been derived, utilizing the link between time and frequency due to the chirp signal. Mixing two chirp signals leads to two frequency components, their exact frequencies depending on the time offset between the two signals. To determine this time offset, two detection methods are investigated. The first method, positive negative detection (PND), searches for both frequency components, while the second method, maximum power detection (MPD), searches for the strongest frequency component. Next, mapping the algorithm onto hardware was simulated. Relevant parameters and their performance impact were investigated using an design space exploration, to achieve a high performance with minimal hardware requirements. Results show that in ninety percent of the simulations the synchronization error is within the system’s resolution, which is limited by the fast Fourier transform (FFT) resolution. While transmission power was kept at such a level that, to the receiver, the communication signal was buried under the noise floor. The final system consists of a 1 bit analog to digital converter (ADC), a 256 point FFT and uses the MPD method. The PND method showed to be unsuitable, with a correct synchronization performance of only fifty-five percent. Impact on the commu- nication performance, measured via bit error rate (BER) curves, shows a maximum loss of 1 dB in signal to noise ratio (SNR) performance with a data rate of 4 kHz, but can be reduced by in- creasing the bandwidth of the modulation scheme. The proposed algorithm and hardware meet the requirements for speed, accuracy and power requirements. Firstly, as the algorithm requires only one execution, for the duration of half a chirp period. And secondly, the accuracy of the system can be chosen such, that it does not impact the communication performance significantly. Furthermore, recommendations are presented on the type of chirp signals to use. Either one up or down chirp should be used for synchronization. While for communication purposes, a combination of both types should be used to avoid discontinuities in the carrier’s frequency, as these discontinuities, in combination with any synchronization errors, lead to loss of communication. i Acknowledgements Finally. At last I can finish my report and complete my master thesis, ending my time at the Uni- veristy of Twente. I have had a great time during my study, both with studying as well with ac- tivities outside the classroom. For some of these distractions I have to thank Bert Molenkamp, Jan Broenink and Sabih Gerez, it was a learning experience and fun to work for and with you. Before this period of my life ends, I want to use this place to thank the people who helped me during my work on this project. First of all I want to thank my committee: André, Gerard, Ramen and Ronan. Thank you for your feedback, especially André for going through all the paperwork I produced. I would also like to thank my friends and family, for their support and motivational questioning, yes this really is the final version :). Thanks Jos and Ed for reading my report, your suggestions helped me a lot. And finally I want to thank the people at CAES, for creating this pleasant environment to work and be in. René Moll Enschede, Februari 2013 iii Acronyms ADC analog to digital converter. ASIC application-specific integrated circuit. ASK amplitude shift-keying. AWGN additive white gaussian noise. BER bit error rate. BFSK binary frequency shift-keying. BOK binary orthogonal keying. CMOS complementary metal oxide semiconductor. ¡ ¡ CORDIC coordinate rotation digital computer. CPM continuous phase modulation. CW continuous wave. DFT discrete Fourier transform. DM direct modulation. DQPSK differential quadrature phase shift-keying. DSP digital signal processor. FFT fast Fourier transform. FoM figure of merit. FRFT fractional Fourier transform. FSK frequency shift-keying. FWL fractional word length. HBT heterojunction bipolar transistor. IWL integer word length. LFS linear frequency sweep. LO local oscillator. LSB least significant bit. MIPS million instructions per second. MPD maximum power detection. v ACRONYMS NBI narrowband interference. OFDM orthogonal frequency division multiplexing. OSR oversampling ratio. PE processing element. PND positive negative detection. PSD power spectral density. PSK phase shift-keying. RAM random access memory. RISC reduced instruction set computing. SAW surface acoustic wave. SDC serial delay commutator. SFDR spurious free dynamic range. SINR signal to interference plus noise ratio. SIR signal to interference ratio. SNR signal to noise ratio. SQNR signal to quantization noise ratio. UWB ultra wideband. VCO voltage controlled oscillator. vi List of Symbols ¯ Chirp rate 1/Hz. Eb Energy of a signal representing a bit J. Fs Sample frequency Hz. I Discrete information stream in bits to be transmitted. N0 Power spectral density of white noise. N f f t FFT order or number of bins. NQ Power spectral density of quantization noise. Pi Interference power W. Tb Bit period s. Tc Chirp period s. tm Measurement window s. Ts Sample period s. Wc Chrip bandwidth Hz. Wf f t FFT bandwidth Hz. Wres FFT resolution in Hz/bin. vii Contents Abstract i Acknowledgements iii Acronyms iv List of Symbols vii 1 Introduction 1 1.1 Digital communication.................................. 1 1.2 Assignment......................................... 2 1.3 Requirements ....................................... 3 1.4 Structure .......................................... 4 2 Chirped communication5 2.1 Introduction to binary frequency shift-keying .................... 5 2.1.1 Definition..................................... 5 2.1.2 Properties..................................... 6 2.2 Communication model.................................. 8 2.2.1 Components ................................... 8 2.2.2 Modeling the BFSK receiver........................... 10 2.2.3 Effect of interference on the bit error rate .................. 12 2.2.4 Simulation results ................................ 13 2.3 Introducing the chirp signal............................... 14 2.3.1 Definition..................................... 14 2.3.2 Properties..................................... 16 2.3.3 Usage of chirp signals.............................. 16 2.4 Chirped communication model............................. 17 2.4.1 Components ................................... 17 2.4.2 BFSK implementation.............................. 20 2.5 Simulation results..................................... 21 3 The proposed synchronization scheme 23 3.1 Chirp based synchronization in literature....................... 23 3.2 The algorithm ....................................... 23 3.3 Frequency detection ................................... 25 3.3.1 Discrete Fourier Transform........................... 26 3.3.2 Detection methods................................ 27 3.4 Using a up and down chirp combination ....................... 29 3.5 Conclusions ........................................ 30 4 Design of the synchronization module 31 4.1 Baseline model....................................... 32 4.1.1 Simulation method ............................... 32 4.2 Analog to digital converter................................ 34 4.2.1 Background.................................... 35 4.2.2 Resolution..................................... 39 4.2.3 Sampling...................................... 41 viii CONTENTS 4.3 Discrete Fourier transform................................ 43 4.3.1 Background.................................... 43 4.3.2 Resolution and measurement time ...................... 44 4.3.3 Twiddle factors.................................. 48 4.3.4 Implementation ................................. 48 4.3.5 Conclusion .................................... 51 4.4 Control logic........................................ 52 5 Impact on the BER due to imperfect synchronization 53 5.1 Time and frequency offset................................ 53 5.2 Effect of offsets on BFSK modulation.......................... 54 5.3 Effect of offsets on chirped communication...................... 56 5.4 Simulation results..................................... 56 6 Conclusions & Recommendations 59 6.1 Conclusions ........................................ 59 6.2 Recommendations .................................... 60 A Model information 61 A.1 ADC Headroom factor .................................. 61 A.2