Version 3.0 December 1998 2975 Stender Way, Santa Clara, California 95054 Telephone: (800) 345-7015 • TWX: 910-338-2070 • FAX: (408) 492-8674 Printed in U.S.A. © 1998 Integrated Device Technology, Inc. Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc. LIFE SUPPORT POLICY Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the manufacturer and an officer of IDT. 1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sus- tain life and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. The IDT logo is a registered trademark, and BiCameral, BurstRAM, BUSMUX, CacheRAM, DECnet, Double-Density, FASTX, Four-Port, FLEXI-CACHE, Flexi-PAK, Flow-thruEDC, IDT/ c, IDTenvY, IDT/sae, IDT/sim, IDT/ux, MacStation, MICROSLICE, PalatteDAC, REAL8, RC3041, RC3051, RC3052, RC3081, RC36100, RC32364, RC4600, RC4640, RC4650, RC4700, RC5000, RC64474, RC64475, RISController, RISCore, RISC Subsystem, RISC Windows, SARAM, SmartLogic, SyncFIFO, SyncBiFIFO, SPC, TargetSystem and WideBus are trade- marks of Integrated Device Technology, Inc. MIPS is a registered trademark, and RISCompiler, RISComponent, RISComputer, RISCware, RISC/os, R3000, and R3010 are trademarks of MIPS Computer Systems, Inc. Postscript is a registered trademark of Adobe Systems, Inc. AppleTalk, LocalTalk, and Macintosh are registered trademarks of Apple Computer, Inc. Centronics is a registered trademark of Genicom, Inc. Ethernet is a registered trademark of Digital Equipment Corp. PS2 is a registered trademark of IBM Corp. This manual provides a reference for all real hardware (non-synthetic) assembler instructions. A sister publication of this manual provides an introduction and design overview as well as more detailed descriptions for the following IDT product families: ◆ IDT79RC30xx family of 32-bit RISC controllers ◆ IDT79RC323xx family of 32-bit enhanced MIPS-2 embedded devices ◆ IDT79RC4xxx 64-BIT RISCONTROLLER family of high-performance 64-bit CPUs ◆ IDT79RC5000 family of MIPS-4 ISA compatible CPU devices Chapter 1, “CPU Instructions Basics,” presents an overview and broad classification of the CPU instruction set of all IDT microprocessors and RISControllers. Chapter 2, “CPU Instructions Reference,” is the detailed reference material for each of the CPU instructions in alphabetical order. Each new instruction starts on a new page and the instruction mnemonic is easily locatable at the top of the page in large bold letters. Chapter 3, “CPU instructions Encoding,” explains the format and encoding of all of the CPU instructions. Chapter 4, “FPU Instructions Basics,” is similar to Chapter 1 except that it deals with the FPU (hardware floating point unit) instructions. Chapter 5, “FPU Instructions Reference,” is similar to Chapter 2 except that it deals with the FPU (hardware floating point unit) instructions. Chapter 6, “FPU instructions Encoding,” is similar to Chapter 3 except that it deals with the FPU (hardware floating point unit) instructions. About This Manual 1 About This Manual 2 CPU Instructions Basics Introduction .......................................................................................................................... 1-1 Functional Instruction Groups .............................................................................................. 1-1 Load and Store Instructions ...................................................................................... 1-2 Delayed Loads .......................................................................................................... 1-3 CPU Loads and Stores ............................................................................................. 1-3 Atomic Update Loads and Stores ............................................................................. 1-4 Coprocessor Load and Store Instructions ................................................................. 1-4 Computational Instructions .................................................................................................. 1-4 Arithmetic Logic Unit ................................................................................................. 1-4 Shift Instructions ....................................................................................................... 1-5 Multiply and Divide Instructions ................................................................................ 1-6 Jump and Branch Instructions .................................................................................. 1-6 Miscellaneous Instructions ................................................................................................... 1-8 Exception Instructions ............................................................................................... 1-8 Serialization Instructions ........................................................................................... 1-8 Conditional Move Instructions ................................................................................... 1-8 Prefetch Instructions ................................................................................................. 1-9 Coprocessor Instructions ..................................................................................................... 1-9 Coprocessor Load and Store Instructions ............................................................... 1-10 Coprocessor Operations ......................................................................................... 1-10 Memory Access Types ....................................................................................................... 1-10 Uncached ................................................................................................................ 1-10 Cached Noncoherent .............................................................................................. 1-10 Cached Coherent .................................................................................................... 1-10 Cached .................................................................................................................... 1-10 Mixing References with Different Access Types ................................................................ 1-10 Cache Coherence Algorithms and Access Types .............................................................. 1-11 Implementation-Specific Access Types ............................................................................. 1-11 Instruction Descriptions ...................................................................................................... 1-12 Instruction Mnemonic and Name ............................................................................ 1-12 Instruction Encoding Picture ................................................................................... 1-12 Format ..................................................................................................................... 1-13 Purpose ................................................................................................................... 1-13 Description .............................................................................................................. 1-13 Restrictions ............................................................................................................. 1-13 Operation ................................................................................................................ 1-13 Exceptions .............................................................................................................. 1-14 Programming and Implementation Notes ............................................................... 1-14 Operation Section Notation and Functions ............................................................. 1-14 Pseudocode Language ........................................................................................... 1-14 Pseudocode Symbols ............................................................................................. 1-14 Pseudocode Functions ...................................................................................................... 1-16 Coprocessor General Register Access Functions ............................................................. 1-16 Load and Store Memory Functions ...................................................................................