Eindhoven University of Technology MASTER Power modeling and analysis of exascale systems Poddar, S. Award date: 2016 Link to publication Disclaimer This document contains a student thesis (bachelor's or master's), as authored by a student at Eindhoven University of Technology. Student theses are made available in the TU/e repository upon obtaining the required degree. The grade received is not published on the document as presented in the repository. The required complexity or quality of research of student theses may vary by program, and the required minimum study period may vary in duration. General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain Department of Mathematics and Computer Science Groene Loper 5, 5612 AZ Eindhoven P.O. Box 513, 5600 MB Eindhoven The Netherlands Series Title: Master graduation thesis, Embedded Systems Power modeling and analysis of Commissioned by Professor: exascale systems prof.dr. H. (Henk) Corporaal Group / Chair: Electronic Systems Date of final presentation: by August 15, 2016 Date of publishing: Author: Sandeep Poddar August 31, 2016 Student id: 0926459 Report number: (Optional for groups) Internal supervisors: prof.dr. H. (Henk) Corporaal External supervisors: ir. Rik Jongerius (IBM) dr. Leandro Fiorin (IBM) Disclaimer The Department of Mathematics and Computer Science of the Eindhoven University of Technology accepts no responsibility for the contents of M.Sc. thesis or practical training Where innovation starts reports. Power modeling and analysis of exascale systems • i Abstract In 1937, Grote Reber built the world's first radio telescope and since then the designs of radio telescopes have developed considerably|ranging from single aperture telescopes to telescopes consisting of large arrays of many receivers. Driven by science case and the resulting scientific requirements, the astronomical com- munity is now designing the world's largest and most sensitive telescope, called the Square Kilometre Array (SKA). When build, this telescope will generate a massive amount of data which has to be processed in near real-time. The processing will require a compute capability of at least one exaflop per second, and it needs to be done within a limited power budget set by the SKA Organisation. To meet the demands of the telescope, we need to design future high-performance workload-optimized com- puting systems. In addition, due to stringent cost and power budgets, power-aware system modeling has become an essential aspect for designing future exascale systems. In order to co-design software and hard- ware systems, system architects require a comprehensive infrastructure to explore different designs, and meet the required energy efficiency. Exabounds is an analytical performance model that provides such an infras- tructure and facilitates designing of future exascale systems. For a holistic design process, power modeling is important as well and needs to be incorporated in the ExaBounds framework. In this context, the goal of this thesis is to propose and implement a methodology for power modeling of processors and DRAM memory in ExaBounds, and use it in the overall design analysis of future exascale system for the SKA. In literature, various power models of processors and DRAMs exist. However, recent studies have questioned the reliability and accuracy of existing power models. Keeping this in mind, and based on ExaBounds require- ments on power models, this research evaluates and validates existing processor power models and DRAM power models for current state-of-the-art technologies. We evaluate two DRAM power models (CACTI and DRAMPower). The CACTI results show a low accuracy of about 50% for DDR4. In contrast, DRAMPower is about 78% accurate, however it requires a memory trace, which is not available in the ExaBounds frame- work. As a consequence, we propose a memory scheduler agnostic power model for DRAM (MeSAP), while relying for the processor power model on McPAT by Li et al. [2009], an existing architecture-level power model, although, results indicate that accuracy of McPAT vary with the target processor architecture under study. For Intel architectures, McPAT by Li et al. [2009] is a better choice, while for IBM architecture, an improved version of McPAT by Xi et al. [2015] is more accurate. MeSAP is based on JEDEC standard current and timing parameters. It is memory scheduler agnostic, and hence does not require a memory trace for power estimation. Instead, it uses limited statistics such as number of bytes read and written to DRAM amongst others. The model is based on a close-page policy, and a simpli- fied power state transition diagram of DRAM. We validate the model against measurements for DDR3 and DDR4 memories. On average, we observed an error in the range of 15-25%. We also evaluate the implication of using limited statistics in contrast to a detailed memory trace. We observed that a cycle-accurate DRAM This work was conducted in the context of the joint ASTRON and IBM DOME project and was funded by the Dutch Ministry of Economische Zaken, and the Province of Drenthe. It was carried out at IBM Research, The Netherlands. c Sandeep Poddar 2016. All rights are reserved. Reproduction in whole or in part is prohibited without the written consent of the copyright owner. Embedded systems master's thesis. ii • S. Poddar power model captures the dynamic behaviour in an application more accurately but it is time consuming. We study the impact of using statistics from two different performance modeling frameworks: a cycle-accurate performance model (GEM5), and an analytical performance model (ExaBounds). We observed that power estimation accuracy of MeSAP depends on how accurate a performance modeling framework predicts DRAM throughput of an application. Moreover, to facilitate design-space exploration of current and future DRAM architectures, we integrate the DRAMSpec tool with MeSAP. The DRAMSpec tool provides an infrastruc- ture to generate JEDEC standard current and timing parameters of different DRAM designs for memory technology like DDR3 and hybrid memory cube. Using the proposed power modeling methodology in ExaBounds, we perform a design-space exploration to search the most energy efficient combination of processor and DRAM design for the science data processor (SDP) of the SKA. We do this for two key algorithms in the SDP pipeline: the gridding algorithm and the two-dimensional FFT. The extrapolation model in the ExaBounds framework scales the application prop- erties to exascale, which enables us to perform analysis for an exascale system. We observed that not only the processor configuration, but also different DRAM architectures influence energy consumption, and hence affects design choices for an energy-efficient exascale system. Using the most energy-efficient design point from the results of the design-space exploration, we predict the total power consumption and DRAM power consumption for the two SKA phase 1 instruments (SKA1-Low, and SKA1-Mid). We do this for the combined execution of the gridding algorithm and the 2D FFT algorithm in the SDP pipeline with the assumption that the two algorithms execute sequentially. For SKA1-Low, the two algorithms combined will consume about 1.85 MW power, out of which the DRAM power consumption amounts to about 0.12 MW. For SKA1-Mid, the two algorithms combined will consume about 250.1 MW in total, and out of this 44.86 MW will be consumed by the DRAM. It is to note that the two algorithms are responsible for 34% of the computing load of the SDP, and the power prediction is a worst-case power consumption as it is for imaging with the full instrument at the full bandwidth and with the full resolution. The work concerning validation and evaluation of power models is beneficial to system architects as it brings out existing accuracies or inaccuracies in the power modeling tools, and will prevent them to derive incorrect conclusions. The modeling methodology proposed benefits ExaBounds users for designing of future energy efficient exascale systems. The design analysis for the science data processor (SDP) of the SKA at exascale gives an idea to the SKA community regarding the power requirements. An analysis such as this will drive future research and innovation towards energy efficient and workload-specialized computing for exascale. Embedded systems master's thesis. Power modeling and analysis of exascale systems • iii Acknowledgements I would like to first thank the members of my thesis committee - not only for their time and patience, but for their intellectual contributions to my development. To prof.dr. Henk Corporaal, who is also my supervisor at the university, I thank for his invaluable guidance and feedback throughout, and for his confidence in my abilities. To ir. Rik Jongerius, who is also my supervisor at IBM, I thank for always appreciating every small idea and work that I proposed and spending incalculable hours evaluating and reviewing them, for constantly encouraging me to improve my work, and for spending time reviewing this thesis and providing useful advice to scientific writing. To dr. Leandro Fiorin, who is also my co-supervisor at IBM, I thank for his invaluable inputs, guidance and encouragement, and for spending time reading this thesis and providing useful suggestions. To dr.ir. Richard Verhoeven, whom I am most appreciative for agreeing to serve on the committee on short notice, and for his inputs during the intermediate presentation. I would also like to convey my sincere thanks to my colleagues and seniors at IBM, namely dr.