DSP56800 Family Manual 16-Bit Digital Signal Controllers DSP56800FM Rev. 3.1 11/2005 freescale.com Contents Chapter 1 Introduction 1.1 DSP56800 Family Architecture . .1-1 1.1.1 Core Overview . .1-2 1.1.2 Peripheral Blocks . .1-3 1.1.3 Family Members . .1-5 1.2 Introduction to Digital Signal Processing. .1-5 1.3 Summary of Features . .1-9 1.4 For the Latest Information . .1-10 Chapter 2 Core Architecture Overview 2.1 Core Block Diagram . .2-1 2.1.1 Data Arithmetic Logic Unit (ALU) . .2-3 2.1.2 Address Generation Unit (AGU) . .2-3 2.1.3 Program Controller and Hardware Looping Unit . .2-4 2.1.4 Bus and Bit-Manipulation Unit. .2-5 2.1.5 On-Chip Emulation (OnCE) Unit . .2-5 2.1.6 Address Buses. .2-5 2.1.7 Data Buses . .2-5 2.2 Memory Architecture . .2-6 2.3 Blocks Outside the DSP56800 Core. .2-7 2.3.1 External Data Memory . .2-7 2.3.2 Program Memory . .2-8 2.3.3 Bootstrap Memory . .2-8 2.3.4 IP-BUS Bridge . .2-8 2.3.5 Phase Lock Loop (PLL) . .2-8 2.4 DSP56800 Core Programming Model . .2-8 Chapter 3 Data Arithmetic Logic Unit 3.1 Overview and Architecture. .3-2 3.1.1 Data ALU Input Registers (X0, Y1, and Y0) . .3-4 3.1.2 Data ALU Accumulator Registers . .3-4 3.1.3 Multiply-Accumulator (MAC) and Logic Unit . .3-5 3.1.4 Barrel Shifter. .3-5 3.1.5 Accumulator Shifter . .3-6 3.1.6 Data Limiter and MAC Output Limiter . .3-6 Freescale Semiconductor iii 3.2 Accessing the Accumulator Registers . .3-7 3.2.1 Accessing an Accumulator by Its Individual Portions . .3-8 3.2.2 Accessing an Entire Accumulator. .3-10 3.2.2.1 Accessing for Data ALU Operations . .3-10 3.2.2.2 Writing an Accumulator with a Small Operand . .3-10 3.2.2.3 Extension Registers as Protection Against Overflow . .3-10 3.2.2.4 Examples of Writing the Entire Accumulator . .3-11 3.2.3 General Integer Processing . .3-11 3.2.3.1 Writing Integer Data to an Accumulator . .3-11 3.2.3.2 Reading Integer Data from an Accumulator. .3-12 3.2.4 Using 16-Bit Results of DSC Algorithms. .3-12 3.2.5 Saving and Restoring Accumulators. .3-12 3.2.6 Bit-Field Operations on Integers in Accumulators . .3-13 3.2.7 Converting from 36-Bit Accumulator to 16-Bit Portion . .3-13 3.3 Fractional and Integer Data ALU Arithmetic . .3-14 3.3.1 Interpreting Data . .3-16 3.3.2 Data Formats. .3-17 3.3.2.1 Signed Fractional . .3-17 3.3.2.2 Unsigned Fractional . .3-17 3.3.2.3 Signed Integer . .3-18 3.3.2.4 Unsigned Integer. .3-18 3.3.3 Addition and Subtraction . .3-18 3.3.4 Logical Operations . .3-19 3.3.5 Multiplication . .3-19 3.3.5.1 Fractional Multiplication . .3-19 3.3.5.2 Integer Multiplication . .3-20 3.3.6 Division. .3-21 3.3.7 Unsigned Arithmetic. .3-22 3.3.7.1 Conditional Branch Instructions for Unsigned Operations. .3-22 3.3.7.2 Unsigned Multiplication . .3-22 3.3.8 Multi-Precision Operations. .3-23 3.3.8.1 Multi-Precision Addition and Subtraction . .3-23 3.3.8.2 Multi-Precision Multiplication . .3-23 3.4 Saturation and Data Limiting . .3-26 3.4.1 Data Limiter . .3-26 3.4.2 MAC Output Limiter . .3-28 3.4.3 Instructions Not Affected by the MAC Output Limiter . .3-29 3.5 Rounding. .3-30 3.5.1 Convergent Rounding . .3-30 3.5.2 Two’s-Complement Rounding . .3-31 3.6 Condition Code Generation . .3-33 3.6.1 36-Bit Destinations — CC Bit Cleared. .3-33 3.6.2 36-Bit Destinations — CC Bit Set . .3-34 3.6.3 20-Bit Destinations — CC Bit Cleared. .3-34 3.6.4 20-Bit Destinations — CC Bit Set . .3-34 3.6.5 16-Bit Destinations . .3-35 3.6.6 Special Instruction Types . .3-35 iv DSP56800 Family Manual Freescale Semiconductor 3.6.7 TST and TSTW Instructions. .3-36 3.6.8 Unsigned Arithmetic. .3-36 Chapter 4 Address Generation Unit 4.1 Architecture and Programming Model . .4-2 4.1.1 Address Registers (R0-R3) . .4-4 4.1.2 Stack Pointer Register (SP). .4-4 4.1.3 Offset Register (N) . .4-4 4.1.4 Modifier Register (M01). .4-5 4.1.5 Modulo Arithmetic Unit . .4-5 4.1.6.