A C Compiler for a Processor with a Reconfigurable Functional Unit Alex Ye, Nagaraj Shenoy, Scott Hauck, Prithviraj Banerjee Department of Electrical and Computer Engineering, Northwestern University Evanston, IL 60201, USA Abstract With the flexibility of the FPGA, reconfigurable small, which means that they are benefiting directly systems are able to get significant speedups for some from the fast communication between the RFU and the applications. Several architectures have been proposed host processor. This suggests that for some applications to integrate a processor with an FPGA in the same chip it is good to have a simpler FPGA with a faster [1][2][3][5]. The usage of the FPGA can be divided into communication. Furthermore, most of the short two categories: FPGA as a coprocessor or FPGA as a sequences are from complex address calculations. This functional unit [1][5]. The first scheme builds a large indicates that this system has a wider application area FPGA as a coprocessor [2][3]. The FPGA is usually than those of the typical reconfigurable systems, since equipped with some extra hardware to perform control many other applications have complex address flow operations and access memory. The tradeoff is less calculations. host processor area and larger communication overhead Compared to other Processor/FPGA works such as with the host processor. The second scheme builds a Garp[2], Napa [3], PRISC[5], etc, our system and relatively simple FPGA as a reconfigurable functional PRISC are in the functional unit scheme category, while unit (RFU). The function of the FPGA is less than the Garp and Napa belongs to the coprocessor scheme coprocessor scheme. On the other hand, the host category. Garp and Napa target large portions of a processor gets more space and the FPGA gets a faster program that can be implemented in the FPGAs. communication with the host. Usually a large portion will contain some instructions This paper talks about a C compiler for Chimaera, that cannot be implemented in the FPGA. As a result, which is a RISC/RFU architecture. It first describes the users may have to rewrite the program, or the three compilation techniques to extract instruction compiler needs to find a way to execute the program sequences from the applications to put into the RFU. It without touching those instructions. Once such portions then shows some experimental results, which support are found, the compiler has to schedule the both the compiler techniques and the architecture computations both in time and space. While in our approach. system and PRISC, the compiler’s focus is on how to The first compilation technique is Control create and identify instruction sequences that can be Localization. By changing some branches into a changed into one RFU instruction. When the macroinstruction, several basic blocks can be combined instructions are found, the compiler has to generate their into a large basic block. This increases the possibility of mapping in the RFU. There is no need to schedule. Our finding to find more sequences of instructions to put work differs from PRISC mainly in the host processor into the RFU. The second one is SIMD Within A part. The host processor in PRISC is a single-pipelined Register (SWAR) optimization. The SWAR concept one. The major optimization of its compiler is a control divides a register into several fields and performs flow conversion, which is not efficient in current several field-by-field operations in parallel. Most of the architectures. The reason is that most of current contemporary processors support a subset of SWAR in architectures have branch prediction and can handle the form of multimedia extensions, such as Intel MMX, control flow operations better. In our system, we will MIPS VIS, etc. The SWAR optimization in our consider the host to be a more advanced one. Therefore, compiler creates large instruction sequences to support a our compiler is focused on the tasks that are not well more general SWAR model. The third technique is handled by the advanced processors, e.g. instructions Instruction Combination, which identifies all the with sequential dependencies. possible instruction sequences to put into the RFU. This paper makes three contributions. First, it We have evaluated the system through a set of describes two techniques that can effectively create benchmarks. The results demonstrate that although the more and larger instruction sequences for the RFU, RFU doesn’t provide functions for control flow namely Control Localization and SWAR. Second, it operations and memory accesses, the compiler is still shows an algorithm to extract the instruction sequences able to find enough instruction sequences to get in a basic block. Finally, it shows that the instruction significant speedups. The average speedup of all the sequences for the RFU exist in a wide range of benchmarks is 2.6. Sometimes the speedup is as high as applications and the Processor/RFU approach can 7.2. A notable fact is that most of the sequences are achieve significant speedups. 1 Introduction RFUOP can read from all the registers connected to the RFU With the flexibility of the FPGA, reconfigurable systems and then put the result on the result bus. The maximum number are able to get significant speedups for some applications. As of input registers is 9 in Chimaera. Each RFUOP instruction is the general purpose processor and the FPGA each has its own suitable area of applications, several architectures are proposed (Shadow) Register File to integrate a processor with an FPGA in the same chip. The usage of the FPGA in them can be divided into two categories: FPGA as a coprocessor or FPGA as a functional unit. result bus In the coprocessor schemes such as Garp[2] and Napa[3], Host Processor the host processor is coupled with an FPGA based RFU reconfigurable coprocessor. The coprocessor usually has the ability of accessing memory and performing control flow Figure 1. The overall Chimaera architecture operations. There is a communication cost between the associated with a configuration and an ID. For example, an coprocessor and the host processor, which is several cycles or execution sequence “r2=r3<<2; r4=r2+r5; r6=lw 0(r4)” can be more. Therefore, these architectures tend to map a large portion optimized to “r4=RFUOP #1; r6=lw 0(r4)”. Here #1 is the ID of of the application, e.g. a loop, into the FPGA. One calculation this RFUOP and “r5+r3<<2” is the operation of the in the FPGA usually corresponds to a task that takes several corresponding configuration. After an RFUOP instruction is hundred cycles or more. fetched and decoded, the Chimaera processor checks the RFU In the functional unit schemes such as Chimaera[1] and for the configuration corresponding to the instruction ID. If the PRISC[5], the host processor is integrated with an FPGA based configuration is currently loaded in the RFU, the corresponding Reconfigurable Functional Unit (RFU). One RFU Operation output is written to the destination register during the instruction (RFUOP) can take on a task which usually requires several writeback cycle. Otherwise, the processor stalls when the RFU instructions on the host processor. As the functional unit is loads the configuration. interfaced only with the register file, it cannot perform memory operations or control flow operations. The communication is 3 Compiler Implementation faster than the coprocessor scheme. For example, in the We have generated a C compiler for Chimaera which Chimaera architecture, after an RFUOP’s configuration is automatically maps some operations into RFUOPs. The loaded, an invocation of it has no overhead in communication. This gives such architecture a larger range of application. Even C code in cases where only a few instructions can be combined into GCC Parser one RFUOP, we could still apply the optimization if the execution frequency is high enough. In this paper, we talk about a C compiler for a RISC RTL processor with an RFU. The target architecture is Chimaera. GCC Early We describe how the compiler identifies sequences of Optimizations statements in a C program and changes them into RFUOPs. We show the performance benefits that can be achieved by such optimizations over a set of benchmarks. Control Localization The paper is organized into five sections. In Section 2, we give an overview of the Chimaera architecture. Section 3 discusses the compiler organization and implementation in SWAR Chimaera detail. In this section, we first discuss a technique to enhance optimization Optimization the size of the instruction sequence: control localization. Next, we describe the application of the RFU to SIMD Within A Register (SWAR) operations. Lastly, we introduce an Instruction algorithm to identify RFUOPs in a basic block. Section 4 Combination demonstrates some experimental results. We summarize this RTL optimized for paper in Section 5. Chimaera GCC Later 2 Chimaera Architecture Overview Optimizations The overall Chimaera architecture is shown in Figure 1. assembly code with RFUOP The main component of the system is the Reconfigurable RFUOP configuration information Functional Unit, which consists of FPGA-like logic designed to support high-performance computations. It gets inputs from the Figure 2: Phase ordering of the C compiler for Chimaera host processor’s register file, or a shadow register file which duplicates a subset of the values in the host’s register file. generated code is run on a Chimaera simulator. The RFU contains several configurations at the same time. The compiler is built using the widely available GCC An RFUOP instruction will activate the corresponding framework[6]. Figure 2 depicts the phase ordering of the configuration in the RFU. An RFU configuration itself implementation. The C code is parsed into the intermediate determines from which registers it reads its operands.