Rochester Institute of Technology RIT Scholar Works Theses Thesis/Dissertation Collections 5-2006 Quantum and spin-based tunneling devices for memory systems Stephen Sudirgo Follow this and additional works at: http://scholarworks.rit.edu/theses Recommended Citation Sudirgo, Stephen, "Quantum and spin-based tunneling devices for memory systems" (2006). Thesis. Rochester Institute of Technology. Accessed from This Dissertation is brought to you for free and open access by the Thesis/Dissertation Collections at RIT Scholar Works. It has been accepted for inclusion in Theses by an authorized administrator of RIT Scholar Works. For more information, please contact [email protected]. QUANTUM AND SPIN-BASED TUNNELING DEVICES FOR MEMORY SYSTEMS by STEPHEN SUDIRGO A DISSERTATION Submitted in partial fulfillment of the requirements For the degree of Doctor of Philosophy in Microsystems Engineering at the Rochester Institute of Technology May 2006 Author: _________________________________________________________________ Microsystems Engineering Program Certified by: _____________________________________________________________ Santosh K. Kurinec Professor of Microelectronic Engineering Approved by: ____________________________________________________________ Mustafa A.G. Abushagur Director of Microsystems Engineering Program Certified by: _____________________________________________________________ Harvey J. Palmer Dean Kate Gleason College of Engineering NOTICE OF COPYRIGHT © 2006 Stephen Sudirgo REPRODUCTION PERMISSION STATEMENT Permission Granted TITLE: “Quantum and Spin-Based Tunneling Devices for Memory Systems” I, Stephen Sudirgo, hereby grant permission to the Wallace Library of the Rochester Institute of Technology to reproduce my dissertation in whole or in part. Any reproduction will not be for commercial use or profit. Signature of Author: Date: ii DISSERTATION APPROVAL FORM Submitted by Stephen Sudirgo in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Microsystems Engineering and accepted on behalf of the Rochester Institute of Technology by the dissertation committee. We, the undersigned members of the Faculty of the Rochester Institute of Technology, certify that we have advised and/or supervised the candidate on the work described in this dissertation. We further certify that we have reviewed the dissertation manuscript and approve it in partial fulfillment of the requirements of the degree of Doctor of Philosophy in Microsystems Engineering. __________________________________ Committee Chair/Advisor Dr. Santosh K. Kurinec __________________________________ Dr. Sean L. Rommel __________________________________ Dr. Karl D. Hirschman __________________________________ Dr. Syed S. Islam __________________________________ Dr. Chih-Ling Lee __________________________________ Dr. Phillip E. Thompson __________________________________ Microsystems Engineering Director Dr. Mustafa A.G. Abushagur __________________________________ Kate Gleason College of Engineering Dean Dr. Harvey J. Palmer iii ABSTRACT Kate Gleason College of Engineering Rochester Institute of Technology Degree Doctor of Philosophy Program Microsystems Engineering Name of Candidate Stephen Sudirgo Title Quantum and Spin-Based Tunneling Devices for Memory Systems Rapid developments in information technology, such as internet, portable computing, and wireless communication, create a huge demand for fast and reliable ways to store and process information. Thus far, this need has been paralleled with the revolution in solid-state memory technologies. Memory devices, such as SRAM, DRAM, and flash, have been widely used in most electronic products. The primary strategy to keep up the trend is miniaturization. CMOS devices have been scaled down beyond sub-45 nm, the size of only a few atomic layers. Scaling, however, will soon reach the physical limitation of the material and cease to yield the desired enhancement in device performance. In this thesis, an alternative method to scaling is proposed and successfully realized. The proposed scheme integrates quantum devices, Si/SiGe resonant interband tunnel diodes (RITD), with classical CMOS devices forming a microsystem of disparate devices to achieve higher performance as well as higher density. The device/circuit designs, layouts and masks involving 12 levels were fabricated utilizing a process that incorporates nearly a hundred processing steps. Utilizing unique characteristics of each component, a low-power tunneling-based static random access memory (TSRAM) has been demonstrated. The TSRAM cells exhibit bistability operation with a power supply voltage as low as 0.37 V. Various TSRAM cells were also constructed and their latching mechanisms have been extensively investigated. In addition, the operation margins of TSRAM cells are evaluated based on different device structures and temperature variation from room temperature up to 200oC. The versatility of TSRAM is extended beyond the binary system. Using multi-peak Si/SiGe RITD, various multi-valued TSRAM (MV-TSRAM) configurations that can store more than two logic levels per cell are demonstrated. By this virtue, memory density can be substantially increased. Using two novel methods via ambipolar operation and utilization of enable/disable transistors, a six-valued MV-TSRAM cell are demonstrated. A revolutionary novel concept of integrating of Si/SiGe RITD with spin tunnel devices, magnetic tunnel junctions (MTJ), has been developed. This hybrid approach adds non-volatility and multi-valued memory potential as demonstrated by theoretical predictions and simulations. The challenges of physically fabricating these devices have been identified. These include process compatibility and device design. A test bed approach of fabricating RITD-MTJ structures has been developed. In conclusion, this body of work has created a sound foundation for new research frontiers in four different major areas: integrated TSRAM system, MV-TSRAM system, MTJ/RITD-based nonvolatile MRAM, and RITD/CMOS logic circuits. Abstract Approval: Committee Chair _______________________________________ Program Director _______________________________________ Dean KGCOE _______________________________________ iv A tribute of love to my faithful Honey Bee, Renee B. Maneval for her love, encouragement, patience, and relentless support. v ACKNOWLEDGMENT This work is a team effort. The successful completion of this dissertation was made possible through the generous support of Dr. Santosh K. Kurinec, who not only provided the necessary vision and direction but also continuously gave encouragement and morale support. I would also like to thank Dr. Sean L. Rommel for his inspiring leadership. His knowledge on tunnel diodes, consistency, superb communication skill, and positive influence have propelled this project into a higher level. My deep appreciation also goes to Dr. Karl D. Hirschman who has provided a reliable baseline CMOS process. I would like to thank Dr. Syed S. Islam for his valuable feedback from circuit perspective. I also would like to express my gratitude to Dr. Phillip E. Thompson of the Naval Research Lab, Washington, D.C., for growing the tunnel diode layers. He has been literally the backbone of the entire project. I also thank Dr. Paul R. Berger and his graduate students Niu Jin, Ronghua Yu, Jeffrey Daulton, and Song-Young Park at the Ohio State University, Columbus, OH, for their support in providing the tunnel diode design template and performing post-growth thermal anneal. My utmost gratitude also goes to Dr. Chih-ling Lee and Dr. Adrian Devasahayam of Veeco Inc. for their support in the deposition of magnetic tunnel junctions layers. The study of the high temperature effect, mask layout design, and part of the modeling work would not be possible without the help of David J. Pawlik. Shrinivas Pandharpure was very instrumental in characterizing the CMOS devices and taking this project further by demonstrating a tunneling-based analog-to-digital converter. I would like to thank my colleague, Reinaldo A. Vega, for initializing the ideas of ambipolar operations and the usage of enable/disable transistor in multi-valued memory design. The completion of this project would not be possible without the generous support of Semiconductor and Microsystems Fabrication Laboratory (SMFL) staff: Scott Blondell, Thomas Grimsley, Richard Battlagia, Bruce Tolleson, David Yackoff, Sean O’Brien, and John Nash. Special thanks go to Charles Gruener who has given a superb support in fabricating more than 30 various masks used in this study. If not for my parents, Johan and Febiana Sudirgo who stood by me in every stage of my education, who believed in me, and who love me unconditionally, I would not be where I am today. I would like to say my appreciation for friends who have been faithful in supporting me with their prayers and love: Jim and Louise Gleeson, Yat-Wei and Fook-Nee Chan. Finally, I would like to give thanks to my Lord Jesus Christ in whom I find my joy, strength, and purpose. This project is funded by the National Science Foundation through grant ECS- 0196054 and ECS-0501460. vi TABLE OF CONTENT List of Tables ……………………………………………………………………………. xi List of Figures ………………………………………………………………………...… xii List of Abbreviations ………………………………………………………………...…xxii 1. INTRODUCTION …………………………………………………………………… 1 1.1. Historical Trends and Motivations ……………………………………………… 1 1.2. Microsystems as an Alternative Approach to Scaling …………………………... 4 1.3. The Scope and Novelty