TI Designs Memory Emulation Using 1-Wire® Communication Protocol TI Designs Design Features TI Designs provide the foundation that you need • Complete 1-Wire® Protocol Support Assures an including methodology, testing and design files to Easy Transition and Effortless Substitution for quickly evaluate and customize the system. TI Designs Similar EEPROM Devices help you accelerate your time to market. • Uses LPMs to Accomplish an Average Standby Current Consumption of 600 nA in Standby Mode. Design Resources • Design is Achievable On Any MSP430™ FRAM Device and Allows for Flexibility in the Available TIDM- Design Folder 1WIREFREEPROM EEPROM Memory Space MSP-EXP430FR5969 Product Folder • Includes Selectable Operation Modes Such as Dedicated or Parasitic Power • Provided Firmware May be Modified for Use In ASK Our E2E Experts Other 1-Wire Applications WEBENCH® Calculator Tools Featured Applications • Additional Device Memory Storage • Device Identification and Authentication • Personal Electronics Peripherals Allocate FRAM memory and define variables Start of main function No Has a full byte been sent by the master device? Initialize ports, DCO, timers, and Yes registration number No Is the MSP430 set to process a ROM command? CCIxA/B pin Yes Early reset flag? Master VCC Yes MSP430 RPUP DSCHOTTKY No Process ROM function device AVCC/DVCC Enter LPM until the master sends a pulse Process memory function CTANK LPM exit indicates pulse reception No Are the number of interrupts odd? 460 to 600 µs Reset variables and send presence pulse Yes 0 to 15 µs Record bit value and Reset interrupt increment counter counter and flag 50 to 120 µs Increment bit counter An IMPORTANT NOTICE at the end of this TI reference design addresses authorized use, intellectual property matters and other important disclaimers and information. LaunchPad, Studio, EnergyTrace++ are trademarks of Texas Instruments. 1-Wire is a registered trademark of Maxim Integrated Products, Inc. Wurth Electronics is a registered trademark of Mouser Electronics. Panasonic is a trademark of Panasonic Corporation. Samtec is a trademark of Samtec Inc. Stackpole Electronics is a trademark of Stackpole Electronics Inc. Toshiba is a trademark of Toshiba Corporation. All other trademarks are the property of their respective owners. TIDUAL9A–June 2016–Revised July 2016 Memory Emulation Using 1-Wire® Communication Protocol 1 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated System Description www.ti.com 1 System Description The TIDM-1WIREEEPROM is a firmware-based reference design that emulates EEPROM functionality on an MSP430 ferroelectric RAM (FRAM) device which is compatible with the 1-Wire® communication protocol True to its name, the 1-Wire achieves communication between the master and slave devices through a common line that is pulled up by a resistor. By following the 1-Wire protocol, which dictates the speed that the communication must occur, the slave devices influence the polarity of the data line as it is polled by the master. 1-Wire slave devices successfully receive commands and send responses using a single wire. Another unique advantage of this bus system is that it only needs two wires, data and ground, connected between devices with power being sourced directly through the data line. This operating mode is called parasitic power (as compared to the typical dedicated power). To attain parasitic power, insert a Schottky diode and tank capacitor to power the slave device when the data line is actively being pulled low. Through the application of Low Power Modes (LPMs) and FRAM technology, replicating 1-Wire EEPROM capability is possible on an MSP430 device. The replication of the 1-Wire EEPROM capability on an MSP430 device has been tested with an MSP-EXP430FR5969 LaunchPad™ and TM4C129XNCZAD development board, which is used as the 1-Wire master device. Operating inside of LPMs in an efficient manner lets the MSP430FR5969 device employ parasitic power mode or remain with dedicated power mode. The MCU enters a more economical LPM during standby mode where no communication occurs, resulting in the lowest system current consumption possible. The flexibility in allocating FRAM space for EEPROM memory also allows this solution more flexibility and data storage as compared to other available 1-Wire devices. This TI Design contains the resources to imitate 1-Wire EEPROM functionality on an MSP430 FRAM device. This design includes an explanation of both the simple hardware connections needed, and the provided Code Composer Studio™ C-code application firmware. Section 3 and Section 4 explain how to switch between dedicated and parasitic power in both the hardware and software, along with allocating FRAM space for EEPROM memory use. The instructions also help the user to understand the purpose and application of each ROM and memory function command under 1-Wire protocol, as well as how to initiate communication with a target 1-Wire master device. A Saleae logic analyzer was used to test and confirm proper 1-Wire communication protocol between the 1-Wire master and MSP430 FRAM slave device. Several screen shots of the logic analyzer readings have been provided in Section 5 of this guide. Power consumption measurements were taken with a Keysight N670 5B DC power analyzer. CPU and peripheral states were also recorded using EnergyTrace++™ technology software. 1.1 MSP-EXP430FR5969 The MSP-EXP430FR5969 (also called the FR5969 LaunchPad™) is an inexpensive evaluation module for evaluating and applying MSP430 FRAM technology. Beginning development is simple with an onboard eZ-FET emulator used for programming and debugging the MSP430 device, providing back-channel UART through USB to PC, and communicating with EnergyTrace++. Two user buttons and LEDs are incorporated for user interaction without the need for additional hardware. This LaunchPad showcases the MSP430FR5969 16-bit MCU with 64 KB of FRAM, 2 KB of SRAM, CPU speed up to 16 MHz, 5 timer blocks, a 16-channel 12-bit analog-to-digital converter (ADC), and additional digital peripherals including AES256, CRC, MA, and HW MPY32. A 0.1F SuperCap grants the option for stand-alone power, and rapid prototyping is accomplished with the use of 20-pin BoosterPack expansion headers along with a wide range of available plug-in modules encompassed in the BoosterPack ecosystem. The only peripherals used in this reference design are two separate timers. One timer, TA1, is connected to the data line and uses the CCIxA/B functionality to measure pulse widths sent by the master 1-Wire device. This pin must also be able to switch to general-purpose output operation to respond by pulling on the data line. The application firmware supplied with this reference design uses the MSP430FR5969 CCI1A module input signal from TA1 on pin P1.2 to accomplish this task, but in reality the code can be modified to use any CCIxA/B pin. The other timer, TA0, is used for delays and other general clocking mechanisms. The MPU is used to protect the EEPROM memory stored in the FRAM from inadvertent CPU execution, or read and write access. 2 Memory Emulation Using 1-Wire® Communication Protocol TIDUAL9A–June 2016–Revised July 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated www.ti.com Block Diagrams 2 Block Diagrams 2.1 TIDM-1WIREEEPROM System Block Diagram Figure 1 shows a typical connection between a master device and corresponding MSP430 slave device that replicates 1-Wire EEPROM functionality. The AVcc/DVcc pins may alternatively be tied directly to Vcc if dedicated power mode is desired in the place of parasitic power mode. Figure 1. TIDM-1WIREFREEPROM System Block Diagram 2.1.1 MSP-EXP430FR5969 Functional Diagrams Figure 2 shows the functional diagram of the MSP430FR5869 device. Figure 3 shows the functional diagram for the MSP-EXP430DF5969 LaunchPad board. The upper half of the dotted line represents the eZ-FET, and the bottom half of the dotted line represents the target connections. P1.x, P2.x P3.x, P4.x PJ.x 2x8 2x8 1 x 8 LFXIN, LFXOUT, HFXIN HFXOUT Capacitive Touch IO 0/1 ADC12_B I/O Ports I/O Ports I/O Port MCLK ACLK Comp_E (up to 16 REF_A P1, P2 P3, P 4 PJ Clock standard 2x8 I/Os 2x8 I/Os 1x8 I/Os System (up to 16 inputs, Voltage SMCLK inputs) up to 8 Reference PA PB differential 1x16 I/Os 1x16 I/Os DMA inputs) Controller 3 Channel MAB Bus Control CCIxA/B pin MDB V Logic Master CC D MSP430 MAB device RPUP SCHOTTKY CPUXV2 AVCC/DVCC incl. 16 Registers MPU TA2CTANK AES256 MDB IP Encap Power TA3 Mgmt FRAM RAM Security Watchdog Timer_A CRC16 MPY32 Encryption, LDO 2 CC 64kB 2kB Decryption EEM SVS Registers 48kB 1kB (128, 256) (S: 3+1) 32kB Brownout (int. only) MDB JTAG Interface MAB Spy-Bi-Wire TB0 TA0 TA1 eUSCI_A0 eUSCI_B0 eUSCI_A1 Timer_B Timer_A Timer_A (I2C, RTC_ARTC_B 7 CC 3 CC 3 CC (UART, SPI) Registers Registers Registers IrDA, (int, ext) (int, ext) (int, ext) SPI) LPM3.5 Domain Figure 2. MSP430FR5969 Functional Diagram TIDUAL9A–June 2016–Revised July 2016 Memory Emulation Using 1-Wire® Communication Protocol 3 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Block Diagrams www.ti.com Micro-B LED USB Crystal Red, Green 4 MHz ESD Debug Protection MCU 3.3-V LDO UART, SBW to Target Power to Target 14-pin JTAG header 100-mF Power Selection SuperCap Reset button Crystals HF (MHz) Target Device 20-pin LaunchPad and MSP430FR5969 standard headers 32.768 kHz User Interface 2 buttons and 2 LEDs Figure 3. MSP-EXP430FR5969 Functional Diagram 4 Memory Emulation Using 1-Wire® Communication Protocol TIDUAL9A–June 2016–Revised July 2016 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated www.ti.com Hardware Considerations 3 Hardware Considerations 3.1 Dedicated Power Operation Setting up the MSP-EXP430FR5969 LaunchPad hardware for 1-Wire operation in dedicated power mode needs only three connections: power, ground, and data.