64-Bit Extension Technology Software Developer’s Guide Volume 1 of 2 Revision 1.00 NOTE: The 64-bit extension technology software developer’s guide consists of volumes 1 and 2. Refer to both volumes when evaluating your design needs. Order Number: 300834-001 64-Bit Extension Technology Software Developer’s Guide, Volume 1 of 2 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS. Intel may make changes to specifications and product descriptions at any time, without notice. Developers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Improper use of reserved or undefined features or instructions may cause unpredictable behavior or failure in developer's software code when running on an Intel processor. Intel reserves these features or instructions for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from their unauthorized use. The Intel® IA-32 architecture processors (e.g., Pentium® 4, Intel® XeonTM, and Pentium III processors) may contain design defects or errors known as errata. Current characterized errata are available on request. Intel, Intel386, Intel486, Pentium, Intel Xeon are trademarks or registered trademarks of Intel Corporation and its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. COPYRIGHT © 1997-2004 INTEL CORPORATION ii 64-Bit Extension Technology Software Developer’s Guide, Volume 1 of 2 TABLE OF CONTENTS NOTE: This content listing reflects Volume 1 and Volume 2. Volume 1 houses the TOC, Chapters 1 and 2. Volume 2 houses the rest of the specification. CHAPTER 1 INTRODUCTION 1.1. 64-BIT EXTENSION TECHNOLOGY. 1-1 1.2. OPERATING MODES . 1-1 1.2.1. IA-32e Mode . 1-2 1.2.2. 64-Bit Mode . 1-2 1.2.3. Compatibility Mode . 1-2 1.2.4. Legacy Modes . 1-3 1.2.5. System Management Mode . 1-3 1.3. REGISTER-SET CHANGES . 1-4 1.3.1. General-Purpose Registers (GPRs) . 1-4 1.3.2. Streaming SIMD Extension (SSE) Registers. 1-5 1.3.3. System Registers . 1-5 1.3.3.1. Extended Feature Enable Register (IA32_EFER) . 1-5 1.3.3.2. Control Registers . 1-5 1.3.3.3. Descriptor Table Registers . 1-6 1.3.3.4. Debug Registers. 1-6 1.4. INSTRUCTION-SET CHANGES . 1-7 1.4.1. Address-Size and Operand-Size Prefixes. 1-7 1.4.2. REX Prefixes . 1-8 1.4.2.1. Encoding. 1-8 1.4.2.2. REX Prefix Fields . 1-9 1.4.2.3. Displacement . 1-11 1.4.2.4. Direct Memory-Offset MOVs . 1-12 1.4.2.5. Immediates . 1-12 1.4.2.6. RIP-Relative Addressing . 1-12 1.4.2.7. Default 64-Bit Operand Size. 1-13 1.4.3. New Encodings for Control and Debug Registers. 1-13 1.4.4. New Instructions . 1-13 1.4.5. Stack Pointer . 1-13 1.4.6. Branches . 1-14 1.5. MEMORY ORGANIZATION. 1-14 1.5.1. Address Calculations in 64-Bit Mode . 1-14 1.5.2. Canonical Addressing . 1-15 1.6. OPERATING SYSTEM CONSIDERATIONS. 1-15 1.6.1. CPUID . 1-15 1.6.2. Register Settings and IA-32e Mode . 1-16 1.6.3. Processor Modes . 1-16 1.6.3.1. IA-32e Mode . 1-16 1.6.3.2. Activating IA-32e mode . 1-16 1.6.3.3. Virtual-8086 Mode . 1-17 1.6.3.4. Compatibility Mode . 1-18 1.6.4. Segmentation . 1-18 1.6.4.1. Code Segments . 1-18 1.6.4.2. Segment LOAD Instructions . 1-19 1.6.4.3. System Descriptors . 1-20 1.6.5. Linear Addressing and Paging . 1-21 1.6.5.1. Software Address Translations in 64-Bit Mode . 1-21 1.6.5.2. Paging Data Structures . 1-21 1.6.5.3. Overall Page Protection . 1-25 1.6.5.4. Reserved Bit Checking . 1-25 1.6.6. Enhanced Legacy-Mode Paging . 1-26 1.6.7. CR2 and CR3 . ..