Vivado Design Suite User Guide Implementation UG904 (v2012.4) December 18, 2012 Notice of Disclaimer The information disclosed to you hereunder (the “Materials”) is provided solely for the selection and use of Xilinx products. To the maximum extent permitted by applicable law: (1) Materials are made available "AS IS" and with all faults, Xilinx hereby DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract or tort, including negligence, or under any other theory of liability) for any loss or damage of any kind or nature related to, arising under, or in connection with, the Materials (including your use of the Materials), including for any direct, indirect, special, incidental, or consequential loss or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered as a result of any action brought by a third party) even if such damage or loss was reasonably foreseeable or Xilinx had been advised of the possibility of the same. Xilinx assumes no obligation to correct any errors contained in the Materials or to notify you of updates to the Materials or to product specifications. You may not reproduce, modify, distribute, or publicly display the Materials without prior written consent. Certain products are subject to the terms and conditions of the Limited Warranties which can be viewed at http://www.xilinx.com/warranty.htm; IP cores may be subject to warranty and support terms contained in a license issued to you by Xilinx. Xilinx products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance; you assume sole risk and liability for use of Xilinx products in Critical Applications: http://www.xilinx.com/warranty.htm#critapps. © Copyright 2012 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Vivado, Zynq, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. All other trademarks are the property of their respective owners. Revision History The following table shows the revision history for this document. Date Version Revision 07/25/2012 2012.2 Initial Xilinx release. 08/20/2012 2012.2 Added details of route_design command regarding re-entrant routing and timing constraints. 10/16/2012 2012.3 Added table mapping ISE options to Vivado commands. See Appendix B, ISE Command Map. Added detaills regarding relative paths in the tcl.pre and tcl.post scripts. See Changing Implementation Run Settings in Chapter 1. 11/16/2012 2012.3 Updated route_design example scripts. See Routing in Chapter 3. 12/18/2012 2012.4 Added Incremental Place and Route in Chapter 1. Added Chapter 2, Defining Relatively Placed Macros. Implementation www.xilinx.com 2 UG904 (v2012.4) December 18, 2012 Table of Contents Chapter 1: Implementation Process Implementation Overview . 5 Getting to Implementation . 7 Project and Non-Project Modes . .7 RTL and Synthesized Design . .8 Constraints . .10 Design Checkpoints . .11 Running Implementation in Non-Project Mode . 12 Non-Project Mode Sample Script. .12 Details of Sample Script . .13 Running Implementation in Project Mode. 15 Creating Implementation Runs . .15 Customizing Implementation Strategies . .23 Launching Runs . .28 Running Implementation in Steps . .30 Monitoring the Implementation Run . .30 Determining the Project Status . .32 Incremental Place and Route . 34 Using Incremental Compilation . .36 Moving Forward After Implementation . 39 Viewing Messages . .40 Viewing Implementation Reports . .42 Chapter 2: Defining Relatively Placed Macros Introduction . 46 Assigning Cells to RPM Sets. 46 Assigning Relative Locations . 48 Assigning a Fixed Location to an RPM . 50 Chapter 3: Implementation Commands Introduction . 52 Opening the Synthesized Design. 53 synth_design . 53 read_checkpoint . 54 open_run . 54 link_design . 55 Logic Optimization . 56 opt_design . .56 Implementation www.xilinx.com 3 UG904 (v2012.4) December 18, 2012 Logic Optimization Constraints . .57 Power Optimization. 57 power_opt_design . .58 Placement. 59 place_design . .60 Physical Synthesis . 61 phys_opt_design . .61 Routing . 62 route_design . .62 Appendix A: Using Remote Hosts Launching Runs on Remote Linux Hosts. 65 Configuring Remote Hosts . .65 Setting Up SSH Key Agent Forward. 68 Appendix B: ISE Command Map Tcl Commands and Options. 69 Appendix C: Additional Resources Xilinx Resources . ..