APPLICATION NOTE 81 Application Note 81 Memory Expansion with the High–Speed Microcontroller Family OVERVIEW Probably the biggest obstacle in using a paged memory All members of the High–Speed Microcontroller Family scheme is the placement of the interrupt vector table. are designed to directly address up to 64KB of program During most of the device operation, software can per- and data memory. Occasionally, however, an applica- form an orderly switch between pages. When an inter- tion will require more memory than is either available rupt occurs, however, the device will immediately jump on–chip or through the use of the 64KB memory map. to the appropriate vector address, below 0070h. The The High–Speed Microcontroller Family includes many software has no control over the bank configuration at features which make it easy to address program and/or this point, and the device will attempt to jump to the low data memory greater than 64KB. Bit–addressable I/O end of the cur rent bank to seek the vector table. ports allow s ingle instruction modification of control lines, which can be used to bank switch or page There are two approaches to solving this problem. The between multiple memory devices. The ROMSIZETM simplest is to duplicate the interrupt vector table at the feature allows easy memory resizing for devices with low end of each page. In this way, the interrupt vector on–chip memory. table will be available at all times, regardless of the cur- rent memory configuration. There are a number of dis- This application note discusses the expansion of both advantages to this approach, however. It is an inefficient program and data memory. It is subdivided into three use of program memory as the interrupt vector table main categories: expanding program memory of ROM- (approximately 120 bytes) and often the interrupt ser- less devices beyond 64KB, using the ROMSIZETM fea- vice routines, must be duplicated on every page. Also, ture to expand on-chip program memory up to and some compilers do not directly support duplication of beyond 64KB, and expanding data memory. It begins data across pages, complicating program generation. A with an introduction to bank switching and software sup- more efficient approach is to reserve some lower portion port techniques. of memory, which includes the interrupt vector table, so that it is not paged. This “common area” is directly accessible from any expanded bank without modifica- BANK SWITCHING THEORY tion of the bank selection mechanism. Any time the pro- Expanded memory access beyond 64KB is most fre- cessor performs a code fetch at this common area, quently done through bank switching. This technique hardware forces the memory to access this area, uses one or more general purpose I/O lines as decode regardless of the current page. Careful design will allow lines to address more memory. If a single large–capac- the previous bank address to be saved, so that the ity memory device is used, the additional signals can be device will return automatically when the operation in used directly as address lines. If several smaller capac- the common memory is complete. Interrupt service rou- ity memory devices are used, the signals can be used as tine execution times can be reduced by locating them chip selects. The basic unit of memory switched by the along with the interrupt vector table in the common area decode logic is called a bank or page. For example, if an located at the low end of memory. Most of the examples I/O line was used to switch between two 64KB in this application note designate the lower region of EPROMs, the memory would consist of two 64KB memory as the common area. pages. ECopyright 1995 by Dallas Semiconductor Corporation. 041995 1/13 All Rights Reserved. For important information regarding patents and other intellectual property rights, please refer to Dallas Semiconductor databooks. APPLICATION NOTE 81 SOFTWARE SUPPORT FOR MEMORY pages of code mapped into program space from 8000h EXPANSION to FFFFh. If the designer wished to locate a page at For a paged memory scheme to work, it is necessary to 10000h in the EPROM, he or she would normally select fragment the code into pages and provide a means for an offset of 10000h in the EPROM when loading the file the software to switch between pages. Care must be into the programmer. All addresses in the hex file begin exercised when switching pages that the instruction at 8000h, however, which the device programmer would flow will not be disturbed. There are two main add to 10000h. This would inadvertently place the page approaches to this. The first is to switch pages “on the at 18000h, which was not the intended result. Various fly.” This is demonstrated in the simple page expansion device programmers implement offsets in different example which follows. This approach causes program ways, and the designer is advised to consult the docu- execution to jump directly from one expanded page to mentation accompanying the device programmer for another expanded page. One must exercise caution so the best solution. that the bank switch will occur at a location that corre- sponds to the start of the next instruction in the next bank. Failure to correctly align the instructions may ROMLESS PROGRAM EXPANSION cause the next opcode fetch to occur in the middle of a The absence of on–chip program memory makes multi–byte instruction, resulting in complete loss of pro- expanding the program memory of the DS80C320 rela- gram control. tively simple. Three approaches to expanding program memory are presented here. The first involves expan- A better approach is to change banks from a location sion of relatively small amounts of memory by duplicat- that will be unaffected by the change. This is most often ing vector tables and overlapping pages. The second a common or unpaged location in memory, such as a example uses a common bank for interrupt vectors and reserved location where the interrupt vector table is interrupt service routines, and pages memory using located. Any access to lower memory is automatically several general purpose I/O lines. The last example switched into the common memory by hardware. This uses a latched address to address large amounts of eliminates the code alignment difficulties with the simple memory without using additional general purpose I/O page expansion above, and the need to duplicate inter- lines. rupt vectors and/or interrupt service routines on each memory page. Simple Page Expansion This example shows the simplest way of adding rela- Many compilers and linkers directly support bank tively small amounts of program memory. A single gen- switching, and many of them include library functions for eral purpose I/O line is used to provide up to 128K bytes page switching. The documentation accompanying of program memory. A single 27C010 128K byte your compiler will provide information concerning its EPROM is used, and is divided into two overlapping expanded memory support. Brief examples of assem- memory blocks. One general purpose I/O line, P1.0 in bly language support are listed after some of the exam- this case, is used to provide bank switch control. It is ples below. latched by a 74F74, which is clocked on the rising edge of the PSEN signal. This synchronizes the bank switch Care must be exercised if multiple pages are pro- with the memory cycle. This approach can be extrapo- grammed into a single EPROM. Many EPROM pro- lated to add even greater amounts of memory by using grammers calculate program offsets using the address additional I/O lines. The hardware configuration for this specified in the file, which can lead to misplaced code. example is shown in Figure 1. For example, suppose that a paging scheme involves 041995 2/13 APPLICATION NOTE 81 SIMPLE PAGE EXPANSION EXAMPLE HARDWARE Figure 1 DS80C320 27C010 128K X 8 EPROM P1.0 A16 74F74 PSEN G PORT2 A15–A8 E ALE 74F37 A7–A0 PORT0 LATCH DQ7–D10 The simplicity of the hardware comes at the cost of page, so the interrupt vectors must be available without some software complexity, however. This example uses software intervention. The interrupt vector table con- two banks, both of which contain the interrupt vector sumes approximately 115 bytes from locations 00000h tables in the lower portion of memory. This is necessary to 00070h, and 10000h to 10070h. Additional space because when the device is reset, P1.0 will be high, may be required if duplication of interrupt service rou- forcing the reset vector address to 10000h. Also, an tines is desired on each page. interrupt may occur while executing code from either SIMPLE PAGE EXPANSION EXAMPLE MEMORY MAP Figure 2 1FFFFh BANK 1 0000h – FFFFh 17FFFh INT. VECTORS 0FFFFh BANK 0 07FFFh 0000h – FFFFh INT. VECTORS 00000h 041995 3/13 APPLICATION NOTE 81 This approach is most effective when page switching is The port pin which controls the bank selection will kept to a minimum, i.e. executing straight runs of code. change during the first cycle following MOV instruction. Code efficiency will be improved if the interrupt routines The 74F74 latch causes the new bank selection to be (not just the vectors) are small enough to be duplicated valid on the prefetch during the execution of the second on each page as well. Data tables or strings accessed NOP. The first instruction on the new page must be at with MOVC instructions should be located on the same the address following the second NOP. page as the instruction. There are other ways of modifying port pins, and this This approach directly modifies the page without modi- scheme will work with 2 cycle instructions such as MOV fying the program counter.