Pseudo-nMOS Logic ( Ratioed Logic) 10: Circuit Families 1 Introduction • What makes a circuit fast? – I = C dV/dt -> tpd (C/I) DV – low capacitance – high current – small swing B 4 • A 4 Logical effort is proportional to C/I Y • pMOS are the enemy! 1 1 – High capacitance for a given current • Can we take the pMOS capacitance off the input? • Various circuit families try to do this… 10: Circuit Families 2 Ratioed Logic VDD VDD VDD Resistive Depletion PMOS Load RL Load VT < 0 Load VSS F F F In1 In1 In1 In2 PDN In2 PDN In2 PDN In3 In3 In3 VSS VSS VSS (a) resistive load (b) depletion load NMOS (c) pseudo-NMOS Goal: to reduce the number of devices over complementary CMOS 3 Ratioed Logic VDD • N transistors + Load Resistive • V = V Load OH DD RL R • VOL = PN F RPN + RL In1 • Assymetrical response In2 PDN In3 • Static power consumption • tpL= 0.69 RLCL VSS 4 Active Loads VDD VDD Depletion PMOS Load VT < 0 Load VSS F F In1 In1 In2 PDN In2 PDN In3 In3 VSS VSS depletion load NMOS pseudo-NMOS 5 Pseudo-nMOS • In the old days, nMOS processes had no pMOS – Instead, use pull-up transistor that is always ON • In CMOS, use a pMOS that is always ON – Ratio issue 1.8 – Make pMOSload about ¼ effective1.5 strength of P/2 1.2 pulldown network P = 24 V Ids out 0.9 Vout 0.6 P = 14 16/2 0.3 P = 4 Vin 0 0 0.3 0.6 0.9 1.2 1.5 1.8 Vin 10: Circuit Families 6 Pseudo-nMOS 10: Circuit Families 7 Pseudo-NMOS VTC 10: Circuit Families 8 Pseudo-nMOS Design Static Power Size of PMOS V t OL Dissipation pLH 4 0.693 V 564 mW 14 ps 2 0.273 V 298 mW 56 ps 1 0.133 V 160 mW 123 ps 0.5 0.064 V 80 mW 268 ps 0.25 0.031 V 41 mW 569 ps 10: Circuit Families 9 Pseudo-nMOS Gates • Design for unit current on output Y to compare with unit inverter. inputs • pMOS fights nMOS f • Iout = 4I/3 – I/3 Inverter NAND2 NOR2 gu = gu = gu = g = g = g = d Y d d g = g = g = avg A avg avg Y pu = pu = Y pu = A pd = B pd = A B pd = pavg = pavg = pavg = 10: Circuit Families 10 Pseudo-nMOS Gates • Design for unit current on output Y to compare with unit inverter. inputs • pMOS fights nMOS f Inverter NAND2 NOR2 gu = 4/3 gu = 8/3 gu = 4/3 g = 4/9 2/3 g = 8/9 g = 4/9 d Y d d g = 8/9 g = 16/9 2/3 g = 8/9 2/3 avg A 8/3 avg avg Y pu = 6/3 pu = 10/3 Y pu = 10/3 A 4/3 pd = 6/9 B 8/3 pd = 10/9 A 4/3 B 4/3 pd = 10/9 pavg = 12/9 pavg = 20/9 pavg = 20/9 10: Circuit Families 11 Pseudo-nMOS Design • Ex: Design a k-input AND gate using pseudo- nMOS. Estimate the delay driving a fanout of Pseudo-nMOS H In1 1 Y H Ink 1 • G = 1 * 8/9 = 8/9 4 2Hk 8 13 • F = GBH = 8H/9 39 • P = 1 + (4+8k)/9 = (8k+13)/9 • N = 2 1/N 10:• CircuitD Families= NF + P = 12 Pseudo-nMOS Power • Pseudo-nMOS draws power whenever Y = 0 – Called static power P = IDDVDD – A few mA / gate * 1M gates would be a problem – Explains why nMOS went extinct • Use pseudo-nMOS sparingly for wide NORs • Turn off pMOSen when not in use Y A B C 10: Circuit Families 13 Ratio Example • The chip contains a 32 word x 48 bit ROM – Uses pseudo-nMOS decoder and bitline pullups – On average, one wordline and 24 bitlines are high • Find static power drawn by the ROM – Ion-p = 36 mA, VDD = 1.0 V PVIpull-upDD pull-up 36 μW PPstatic(31 24) pull-up 1.98 mW • Solution: 10: Circuit Families 14 Pseudo-NMOS Design • Pseudo-nMOS gates will not operate correctly if VOL>VIL of the driven gate. • This is most likely in the SF corner. • Conservative design requires extra weak pMOS. • Another choice is to use replica biasing. • Idea comes from analog design. • Replica biasing allows 1/3 the current ratio rather than the conservative ¼ ratio of earlier. 10: Circuit Families 15 Replica Biasing 10: Circuit Families 16 Ganged CMOS 10: Circuit Families 17 Ganged CMOS A B N1 P1 N2 P2 Y 0 0 OFF ON OFF ON 1 0 1 OFF ON ON OFF ~0 1 0 ON OFF OFF ON ~0 1 1 ON OFF ON OFF 0 10: Circuit Families 18 Improved Loads VDD M1 Enable M2 M1 >> M2 F CL A B C D Adaptive Load 19 Improved Loads 10: Circuit Families 20 Improved Loads (2) Differential Cascode Voltage Switch Logic (DCVSL) 21 DCVSL Example Out Out B B B B A A XOR-NXOR gate 22 DCVSL Example 23 DCVSL Transient Response 10: Circuit Families 24 Pass-Transistor Logic B Switch Out A s t Out u p Network B n I B • N transistors • No static consumption 25 Example: AND Gate 10: Circuit Families 26 NMOS-Only Logic 10: Circuit Families 27 NMOS-Only Switch 28 NMOS Only Logic: Level Restoring Transistor • Advantage: Full Swing • Restorer adds capacitance, takes away pull down current at X • Ratio problem 29 Restorer Sizing 10: Circuit Families 30 LEAP • LEAn integration with Pass transistors • Get rid of pMOS transistors – Use weak pMOS feedback to pull fully high – Ratio constraint S A S L Y B 10: Circuit Families 31 .