View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Calhoun, Institutional Archive of the Naval Postgraduate School Calhoun: The NPS Institutional Archive Theses and Dissertations Thesis Collection 2004-03 Network processors and utilizing their features in a multicast design Diler, Timur Monterey, California. Naval Postgraduate School http://hdl.handle.net/10945/1688 MONTEREY, CALIFORNIA THESIS NETWORK PROCESSORS AND UTILIZING THEIR FEATURES IN A MULTICAST DESIGN by Timur DILER March 2004 Thesis Advisor: Su WEN Thesis Co-Advisor: Jon BUTLER Approved for public release; distribution is unlimited THIS PAGE INTENTIONALLY LEFT BLANK REPORT DOCUMENTATION PAGE Form Approved OMB No. 0704-0188 Public reporting burden for this collection of information is estimated to average 1 hour per response, including the time for reviewing instruction, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington, VA 22202-4302, and to the Office of Management and Budget, Paperwork Reduction Project (0704-0188) Washington DC 20503. 1. AGENCY USE ONLY (Leave blank) 2. REPORT DATE 3. REPORT TYPE AND DATES March 2004 COVERED Master’s Thesis 4. TITLE AND SUBTITLE: 5. FUNDING NUMBERS Network Processors and Utilizing their Features in a Multicast Design 6. AUTHOR(S) Timur DILER 7. PERFORMING ORGANIZATION NAME(S) AND ADDRESS(ES) 8. PERFORMING ORGANIZATION Naval Postgraduate School REPORT NUMBER Monterey, CA 93943-5000 9. SPONSORING /MONITORING AGENCY NAME(S) AND ADDRESS(ES) 10. SPONSORING/MONITORING N/A AGENCY REPORT NUMBER 11. SUPPLEMENTARY NOTES The views expressed in this thesis are those of the author and do not reflect the official policy or position of the Department of Defense or the U.S. Government. 12a. DISTRIBUTION / AVAILABILITY STATEMENT 12b. DISTRIBUTION CODE Approved for public release; distribution is unlimited 13. ABSTRACT (maximum 200 words) In order to address the requirements of the rapidly growing Internet, network processors have emerged as the solution to the customization and performance needs of networking systems. An important component in a network is the router, which receives incoming packets and directs them to specific routes elsewhere in the system. Network proces- sors and the associated software control the routers and switches and allow software designers to deploy new systems such as multicasting forwarder and firewalls quickly.This thesis introduces network processors and their features, focusing on the Intel IXP1200 network processor. A multicast design for the IXP1200 using microACE is pro- posed.This thesis presents an approach to building a multicasting forwarder using the IXP1200 network processor layer-3 forwarder microACE that carries out unicast routing. The design is based on the Intel Internet exchange archi- tecture and its active computing element (ACE). The layer-3 unicast forwarder microACE is used as a basic starting point for the design. Some software mo dules, called micoblocks, are modified to create a multicast forwarder that is flexible and efficient. 14. SUBJECT TERMS 15. NUMBER OF IXP1200, multicasting, ACE, microace, network processors, Intel IXA, microengine PAGES 74 16. PRICE CODE 17. SECURITY 18. SECURITY 19. SECURITY 20. LIMITATION OF CLASSIFICATION OF CLASSIFICATION OF THIS CLASSIFICATION OF ABSTRACT REPORT PAGE ABSTRACT Unclassified Unclassified Unclassified UL NSN 7540-01-280-5500 Standard Form 298 (Rev. 2-89) Prescribed by ANSI Std. 239-18 i THIS PAGE INTENTIONALLY LEFT BLANK ii Approved for public release; distribution is unlimited NETWORK PROCESSORS AND UTILIZING THEIR FEATURES IN A MULTICAST DESIGN Timur DILER Lieutenant Junior Grade, Turkish NAVY B.S., Turkish Naval Academy, 1998 Submitted in partial fulfillment of the requirements for the degrees of MASTER OF SCIENCE IN COMPUTER SCIENCE and MASTER OF SCIENCE IN ELECTRICAL ENGINEERING from the NAVAL POSTGRADUATE SCHOOL March 2004 Author: Timur Diler Approved by: Su Wen Thesis Advisor Jon Butler Thesis Co-Advisor John P. Powers Chairman, Department of Electrical and Computer Engi- neering Peter Denning Chairman, Department of Computer Science iii THIS PAGE INTENTIONALLY LEFT BLANK iv ABSTRACT In order to address the requirements of the rapidly growing Internet, network processors have emerged as the solution to the customization and performance needs of networking systems. An important component in a network is the router, which receives incoming packets and directs them to specific routers elsewhere in the system. Network processors and the associated software control the routers and switches and allow soft- ware designers to quickly deploy new systems such as multicasting forwarders and fire- walls. This thesis introduces network processors and their features, focusing on the Intel IXP1200 network processor. A multicast design for the IXP1200 using microACE is pro- posed. This thesis presents an approach to building a multicasting forwarder using the IXP1200 network processor layer -3 forwarder microACE that carries out unicast routing. The design is based on the Intel Internet exchange architecture and its active computing element (ACE). The layer -3 unicast forwarder microACE is used as a basic starting point for the design. Software modules, called micoblocks, are developed to create a multicast forwarder that is flexible and efficient. v THIS PAGE INTENTIONALLY LEFT BLANK vi TABLE OF CONTENTS I. INTRODUCTION ........................................ 1 A. BACKGROUND..................................... 1 B. THESIS PROBLEM STATEMENT........................ 2 C. THESIS OVERVIEW ................................. 2 II. NETWORK PROCESSORS.................................. 5 A. INTRODUCTION.................................... 5 B. THE EVALUATION OF THE NETWORK PROCESSORS ....... 5 1. First-Generation Systems .......................... 6 2. Second-Generation Systems ........................ 7 3. Third-Generation Systems ......................... 8 C. FEATURES OF NETWORK PROCESSORS ................. 9 1. Flexibility with Programmability ..................... 9 2. Scalability ................................... 10 3. Pipelined Processing ............................ 11 4. Parallel Processing.............................. 12 5. Memory Management ........................... 13 D. INTEL EXCHANGE ARCHITECTURE ................... 14 1. Data Plane ................................... 15 2. Control Plane ................................. 15 3. Management Plane ............................. 15 E. SUMMARY....................................... 15 III. INTEL IXP1200 ARHITECTURE............................ 17 A. INTRODUCTION................................... 17 B. OVERVIEW OF IXP1200 ............................. 17 C. IXP1200 COMPONENTS.............................. 18 1. StrongARM Core .............................. 18 2. MicroEngines ................................. 19 3. SRAM and Internal SRAM Interface Unit.............. 24 4. SDRAM and Internal SDRAM Interface Unit ........... 25 5. PCI Unit .................................... 25 D. SUMMARY....................................... 25 IV. IXP1200 PROGRAMMING AND MICROACE STRUCTURE ......... 27 A. INTRODUCTION................................... 27 B. IXP1200 PROGRAMMING ............................ 27 1. Software Development Kit ........................ 28 2. Instruction Set ................................ 29 3. MicroEngine Assembly Syntax ..................... 31 vii 4. Simple Packet Data Flow in IXP1200 ................. 33 C. ACE PROGRAMMING MODEL ........................ 34 1. IXA Application Programming Interface............... 34 2. Active Computing Element ........................ 35 3. MicroACE ................................... 36 4. An Example of MicroACE Processing ................. 37 5. The Dispatch Loop ............................. 38 D. SUMMARY....................................... 39 V. A MULTICASTING FORWARDER DESIGN USING MICROACE ..... 41 A. INTRODUCTION................................... 41 B. MULTICASTING FROM UNICAST FORWARDING.......... 41 C. MULTICASTING FORWARDER MICROACE .............. 43 D. SUMMARY......................................... 49 VI. CONCLUSIONS AND RECOMMENDATIONS ................... 51 LIST OF REFERENCES........................................ 53 INITIAL DISTRIBUTION LIST .................................. 55 viii LIST OF FIGURES Figure 1. Software-Based Architecture. ............................................................................6 Figure 2. Scalability Achievement. .................................................................................11 Figure 3. Parallelism in the IXP1200 NPU. ....................................................................13 Figure 4. IXP1200 Block Diagram (From Ref. 9.). ........................................................18 Figure 5. StrongARM Block Diagram (After Ref. 9.). ...................................................19 Figure 6. MicroEngine Internal Structure (From Ref. 9.). ..............................................20 Figure 7. Thread Context Swapping (From Ref. 9.). ......................................................22 Figure 8. GPR Addressing (From Ref. 9.). .....................................................................23