This Unit: Digital Logic & Hdw Description App App App • Transistors & frabrication System software • Digital logic basics • Focus on useful components CIS 371 Mem CPU I/O Computer Organization and Design • Hardware design methods • Introduction to Verilog Unit 2: Digital Logic & Hardware Description Based on slides by Prof. Amir Roth & Prof. Milo Martin CIS 371 (Martin): Digital Logic & Hardware Description 1 CIS 371 (Martin): Digital Logic & Hardware Description 2 Readings Motivation: Implementing an ISA datapath • Digital logic • P&H, Appendix C (on CD) fetch Insn Register Data PC • Manufacturing memory File Memory • P&H, Section 1.7 control • See webpage for Verilog HDL resources • Datapath: performs computation (registers, ALUs, etc.) • ISA specific: can implement every insn (single-cycle: in one pass!) • Control: determines which computation is performed • Routes data through datapath (which regs, which ALU op) • Fetch: get insn, translate opcode into control • Fetch ! Decode ! Execute “cycle” CIS 371 (Martin): Digital Logic & Hardware Description 3 CIS 371 (Martin): Digital Logic & Hardware Description 4 Two Types of Components Example Datapath datapath fetch Insn Register Data PC memory File Memory control • Purely combinational: stateless computation • ALUs, muxes, control • Arbitrary Boolean functions • Combinational/sequential: storage • PC, insn/data memories, register file • Internally contain some combinational components CIS 371 (Martin): Digital Logic & Hardware Description 5 CIS 371 (Martin): Digital Logic & Hardware Description 6 Semiconductor Technology gate gate insulator source drain source drain Substrate channel channel • Basic technology element: MOSFET • Solid-state component acts like electrical switch • MOS: metal-oxide-semiconductor • Conductor, insulator, semi-conductor • FET: field-effect transistor • Channel conducts source!drain only when voltage applied to gate Transistors & Fabrication • Channel length: characteristic parameter (short ! fast) • Aka “feature size” or “technology” • Currently: 0.032 micron (µm), 32 nanometers (nm) • Continued miniaturization (scaling) known as “Moore’s Law” • Won’t last forever, physical limits approaching (or are they?) CIS 371 (Martin): Digital Logic & Hardware Description 7 CIS 371 (Martin): Digital Logic & Hardware Description 8 Transistor Geometry: Length & Scaling Manufacturing Steps Length" Gate Drain Source Gate Width Source Drain Width" Bulk Si Length Diagrams © Krste Asanovic, MIT • Transistor length: characteristic of “process generation” • 45nm refers to the transistor gate length, same for all transistors • Each process generation shrinks transistor length by 1.4x Source: P&H • Roughly linear improvement in switching speeds (lower resistance) • Roughly 2x improvement in area CIS 371 (Martin): Digital Logic & Hardware Description 9 CIS 371 (Martin): Digital Logic & Hardware Description 10 Manufacturing Steps Integrated Circuit (IC) Costs • Multi-step photo-/electro-chemical process • Chips built in multi-step chemical processes on wafers • More steps, higher unit cost • Cost / wafer is constant, f(wafer size, number of steps) + Fixed cost mass production ($1 million+ for “mask set”) • Chip (die) cost is related to area • Larger chips means fewer of them • Cost is more than linear in area • Why? random defects • Larger chips means fewer working ones • Chip cost ~ chip area#" • # = 2 to 3" • Wafer yield: % wafer that is chips • Die yield: % chips that work • Yield is increasingly non-binary - fast vs slow chips CIS 371 (Martin): Digital Logic & Hardware Description 11 CIS 371 (Martin): Digital Logic & Hardware Description 12 Manufacturing Defects Wires Pitch Correct: • Defects can arise • Under-/over-doping • Over-/under-dissolved insulator • Mask mis-alignment Height Defective: Length • Particle contaminants • Try to minimize defects Width Defective: • Process margins IBM CMOS7, 6 layers of copper wiring • Design rules • Transistors 1-dimensional for design purposes: width • Minimal transistor size, separation • Wires 4-dimensional: length, width, height, “pitch” Slow: • Longer wires have more resistance (slower) • Or, tolerate defects • “Thinner” wires have more resistance (slower) • Redundant or “spare” memory cells • Closer wire spacing (“pitch”) increases capacitance (slower) • Can substantially improve yield CIS 371 (Martin): Digital Logic & Hardware Description 13 CIS 371 (Martin): Digital Logic & Hardware Description From slides © Krste Asanovic, MIT 14 Transistors and Wires Complementary MOS (CMOS) • Voltages as values • Power (VDD) = “1”, Ground = “0” power (1) • Two kinds of MOSFETs p-transistor • N-transistors input output • Conduct when gate voltage is 1 (“node”) • Good at passing 0s n-transistor • P-transistors • Conduct when gate voltage is 0 ground (0) • Good at passing 1s • CMOS • Complementary n-/p- networks form boolean logic (i.e., gates) • And some non-gate elements too (important example: RAMs) ©IBM From slides © Krste Asanovi!, MIT CIS 371 (Martin): Digital Logic & Hardware Description 15 CIS 371 (Martin): Digital Logic & Hardware Description 16 Basic CMOS Logic Gate Another CMOS Gate Example • Inverter: NOT gate • What is this? Look at truth table A B • One p-transistor, one n-transistor • 0, 0 ! 1 • Basic operation 0 • 0, 1 ! 1 output • Input = 0 1 • 1, 0 ! 1 A • P-transistor closed, n-transistor open • 1, 1 ! 0 • Power charges output (1) B • Result: NAND (NOT AND) • Input = 1 • P-transistor open, n-transistor closed • NAND is “universal” • Output discharges to ground (0) A • What function is this? 1 0 B output A B 18 CIS 371 (Martin): Digital Logic & Hardware Description 17 CIS 371 (Martin): Digital Logic & Hardware Description Digital Building Blocks: Logic Gates Alternative to Fabrication: FPGA • Logic gates: implement Boolean functions • We’ll use FPGAs (Field Programmable Gate Array) • Basic gates: NOT, NAND, NOR • Also called Programmable Logic Devices (PLDs) • Underlying CMOS transistors are naturally inverting ( = NOT) • An FPGA is a special type of programmable chip NOT (Inverter) NAND NOR • Conceptually, contains a grid of gates A A A A’ (AB)’ (A+B)’ • The wiring connecting them can be reconfigured electrically B B • Using more transistors as switches • Once configured, the FPGA can emulate any digital logic design • NAND, NOR are “Boolean complete” • Tool converts gate-level design to configuration BUF AND OR A A A A AB A+B • Uses B B • Hardware prototyping (what “we” are doing) AND3 ANDNOT XOR • Low-volume special-purpose hardware A A A • New: computational offload AB’ AB’+A’B B B B C (A^B) CIS 371 (Martin): Digital Logic & Hardware Description 19 CIS 371 (Martin): Digital Logic & Hardware Description 20 In Our Lab: Digilent XUP-V2P Boards • Program FPGA to run LC4 • “The project” • Hook up keyboard • And VGA • Game on! • Boards have many features • Use some for debugging • LEDs, switches Digital Logic Review • Others, not at all • Ethernet, flash reader • 256MB SDRAM, audio in/out • Can boot Linux! CIS 371 (Martin): Digital Logic & Hardware Description 21 CIS 371 (Martin): Digital Logic & Hardware Description 22 Digital Building Blocks: Logic Gates Boolean Functions and Truth Tables • Logic gates: implement Boolean functions • Any Boolean function can be represented as a truth table • Basic gates: NOT, NAND, NOR • Truth table: point-wise input ! output mapping • Underlying CMOS transistors are naturally inverting ( = NOT) • Function is disjunction of all rows in which “Out” is 1 NOT (Inverter) NAND NOR A,B,C ! Out A A A A’ (AB)’ (A+B)’ 0,0,0 ! 0 B B 0,0,1 ! 0 0,1,0 ! 0 • NAND, NOR are “Boolean complete” 0,1,1 ! 0 1,0,0 ! 0 BUF AND OR 1,0,1 ! 1 A A A A AB A+B 1,1,0 ! 1 B B 1,1,1 ! 1 AND3 ANDNOT XOR A A A • Example above: Out = AB’C + ABC’ + ABC AB’ AB’+A’B B B B C (A^B) CIS 371 (Martin): Digital Logic & Hardware Description 23 CIS 371 (Martin): Digital Logic & Hardware Description 24 Truth Tables and PLAs PLA Example • Implement Boolean function by implementing its truth table • PLA with 3 inputs, 2 outputs, and 4 product terms • Takes two levels of logic • Out0 = AB’C + ABC’ + ABC • Assumes inputs and inverses of inputs are available (usually are) A • First level: ANDs (product terms) Permanent • Second level: ORs (sums of product terms) B connections C • PLA (programmable logic array) Programmable • Flexible circuit for doing this connections (unconnected) Out0 Out1 CIS 371 (Martin): Digital Logic & Hardware Description 25 CIS 371 (Martin): Digital Logic & Hardware Description 26 Boolean Algebra Logic Minimization • Boolean Algebra: rules for rewriting Boolean functions • Logic minimization • Useful for simplifying Boolean functions • Iterative application of rules to reduce function to simplest form • Simplifying = reducing gate count, reducing gate “levels” • There are tools for automatically doing this • Rules: similar to logic (0/1 = F/T) Out = AB’C + ABC’ + ABC • Identity: A1 = A, A+0 = A Out = A(B’C + BC’ + BC) // distributivity • 0/1: A0 = 0, A+1 = 1 Out = A(B’C + (BC’ + BC)) // associativity • Inverses: (A’)’ = A Out = A(B’C + B(C’+C)) // distributivity (on B) • Idempotency: AA = A, A+A = A Out = A(B’C + B1) // tautology • Tautology: AA’ = 0, A+A’ = 1 Out = A(B’C + B) // 0/1 • Commutativity: AB = BA, A+B = B+A Out = A((B’+B)(C+B)) // distributivity (on +B) • Associativity: A(BC) = (AB)C, A+(B+C) = (A+B)+C Out = A(1(B+C)) // tautology • Distributivity: A(B+C) = AB+AC, A+(BC) = (A+B)(A+C) Out = A(B+C) // 0/1 • DeMorgan’s: (AB)’ = A’+B’, (A+B)’ = A’B’ CIS 371 (Martin): Digital Logic & Hardware Description