Architecture Description and Packing for Logic Blocks with Hierarchy, Modes and Complex Interconnect Jason Luu, Jason Anderson, and Jonathan Rose The Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto, Toronto, ON, Canada jluu|janders|[email protected] SRHI D SRLO Reset Type INIT1 Q CE Sync/Async ABSTRACT COUT INIT0 CK SR FF/LAT DX The development of future FPGA fabrics with more sophis- DMUX DI2 D6:1 A6:A1 W6:W1 D ticated and complex logic blocks requires a new CAD flow D O6 FF/LAT O5 DX INIT1 Q DQ D INIT0 CK DI1 SRHI that permits the expression of that complexity and the abil- CE SRLO WEN MC31 SRHI D SRLO CK Q SR DI INIT1 CE INIT0 ity to synthesize to it. In this paper, we present a new logic CK SR CX CMUX block description language that can depict complex intra- DI2 C6:1 A6:A1 W6:W1 C C O6 block interconnect, hierarchy and modes of operation. These FF/LAT O5 CX INIT1 Q CQ D INIT0 CK DI1 CE SRHI SRLO features are necessary to support modern and future FPGA WEN MC31 SRHI CK D SRLO SR CI INIT1 Q CE INIT0 complex soft logic blocks, memory and hard blocks. The key CK SR BX BMUX part of the CAD flow associated with this complexity is the DI2 B6:1 A6:A1 W6:W1 B B O6 packer, which takes the logical atomic pieces of the complex O5 FF/LAT BX INIT1 Q BQ D DI1 INIT0 CK CE SRHI SRLO WEN MC31 SRHI CK blocks and groups them into whole physical entities. We D SRLO SR BI INIT1 Q CE INIT0 present an area-driven generic packing tool that can pack CK SR AX AMUX the logical atoms into any heterogeneous FPGA described DI2 A6:1 A6:A1 W6:W1 A A O6 in the new language, including many different kinds of soft FF/LAT O5 AX INIT1 Q AQ D INIT0 DI1 CK CE SRHI SRLO and hard logic blocks. We gauge its area quality by compar- WEN MC31 CK SR AI 0/1 ing the results achieved with a lower bound on the number of SR CE CLK blocks required, and then illustrate its explorative capability CK WEN CIN in two ways: on fracturable LUT soft logic architectures, and ug364_03_040209 on hard block memory architectures. The new infrastructure Figure 1: Commercial Virtex-6 logic block attaches to a flow that begins with a Verilog front-end, per- tain computations more efficiently, or store data, or perhaps mitting the use of benchmarks that are significantly larger contain novel soft logic structures. than the usual ones, and can target heterogenous FPGAs. Today’s publicly available FPGA CAD tools lack the abil- ity to target the complexity present in modern commercial Categories and Subject Descriptors architectures - the Altera Stratix IV [1] and Xilinx Virtex B.6.3 [Design Aids]: Hardware description languages, Op- 6 [2] FPGAs contain highly complex soft logic blocks, hard timization memories and mulitpliers. For example, it simply isn’t pos- sible to represent the details of the Virtex-6 logic block, illus- trated in Fig. 1 [3], in the architecture description language General Terms provided in VPR 5.0 [20]. While commercial tools can be Algorithms, Design, Languages, Measurement, Performance used to synthesize to this exact architecture, there is no ca- pability for researchers to explore new issues (such as process 1. INTRODUCTION variability) for that device, or to modify important aspects of the architecture. As the semiconductor industry evolves and accounts for Furthermore, the MCNC benchmark circuits [33] often the prohibitive cost of custom chip design and fabrication, used in research are no longer representative of modern or together with the continued exponential growth in logic ca- future FPGA applications because they are no larger than a pacity per die, there is a need to make pre-fabricated and few thousand 4-LUTs while commercial FPGAs today can programmable chips more capable. That enhanced capabil- target applications that contain hundreds of thousands and ity may in part be expressed through more complex prog- soon millions or more 4-LUT-equivalents. There is a need, rammable logic blocks. These logic blocks may perform cer- then, for modern, public benchmarks and CAD tools that can deal with the heterogeneity inherent in those bench- Permission to make digital or hard copies of all or part of this work for marks in order to do relevant, scientific research on FPGA personal or classroom use is granted without fee provided that copies are architecture and CAD. not made or distributed for profit or commercial advantage and that copies In this paper, we describe two key new capabilities for an bear this notice and the full citation on the first page. To copy otherwise, to FPGA CAD flow that provide the ability to describe and republish, to post on servers or to redistribute to lists, requires prior specific synthesize for the necessary complexity: first, we present a permission and/or a fee. FPGA’11, February 27–March 1, 2011, Monterey, California, USA. new logic block description language that can express far Copyright 2011 ACM 978-1-4503-0554-9/11/02 ...$10.00. more complex logic blocks than is currently possible with 227 any publicly available toolset. It can describe complex logic get a simple block consisting of a cluster of fully-connected blocks with arbitrary internal routing structures (such as basic logic elements and Ho’s language [13] which describes all the small muxes in Fig. 1), it permits arbitrary levels of more sophisticated floating-point cores as blocks. hierarchy within the logic block and it can give blocks differ- Other languages focus more on expressiveness. Cronquist’s ent modes that represent significantly different functionality Emerald [10], Filho’s CGADL [12], Ebeling’s language for and interconnect of portions of the block. Modern commer- RaPiD [11], and the languages described in [26], use a netlist cial FPGAs have different modes in their memory blocks, representation which, though very expressive, is cumber- for example, they can be configured as say 4Kx8, or 8Kx4, some and verbose when expressing simple soft logic complex or 16Kx2 memories and so on. The new language permits blocks. Paladino proposed a general complex block descrip- the description of an FPGA with many different kinds of tion language called CARCH in [29] which employs proper- blocks, each of which can have the above features. The new ties and rules to gain expressiveness, but was focussed on language also allows the specification of timing for the atoms more microscopic attributes of common soft logic blocks. and their interconnect. Secondly, we present a new area-driven packing frame- 2.2 Packing Algorithms work and algorithm that takes as input a user design as well There is large body of prior work on the packing prob- as an architectural description in the language mentioned lem for FPGAs. Most of it focuses on the optimization of above, and then determines area-efficient legal groupings of area, delay, and/or power for the basic (LUT-based) soft the atoms in the design into the logic blocks specified in the logic complex blocks. These algorithms include T-VPack language. This problem is far more complex than the tradi- [21], T-RPack [7], IRAC [30], HDPack [9], and others [17] tional LUT-packing problem [5] because of the non-simple [18]. Lemieux [16] and Wang [32] investigated packing to a interconnects, hierarchy and modes. Indeed, this kind of basic soft logic complex block that contains a depopulated packing problem contains within it a combined placement crossbar. and routing problem. Fortunately, the packing context per- There has also been work on packing for complex blocks mits some efficiencies which we describe in the paper. that are significantly different from the basic complex block. We illustrate these new capabilities through two architec- Ni proposed an algorithm that packs together netlist blocks tural experiments: one that explores different fracturable for clusters with arbitrary interconnect and an arbitrary LUTs, now commonly used in industry, and one that ex- number of heterogeneous primitives [28]. The algorithm plores different aspects of hard block memory architectures. does not scale and it is intractable to use it to model all In each of these experiments, we use a new set of large-scale but the smallest soft logic clusters. Ahmed described pack- Verilog circuits that contain both memory and multipliers. ing DSP blocks to make use of regularity in placement and This paper is organized as follows: the next section pro- routing [4]. Paladino proposed a design rule check (DRC) vides relevant background; Section 3 describes the new lan- based packer called DC that can pack to the soft logic of guage with examples, and Section 4 gives the generic packing two different Altera FPGA families [29]. Limitations with algorithm. The new features are integrated into an existing the tool prevent it from exploring non-trivial complex blocks FPGA CAD system. Section 5 gives the illustrative archi- such as memories and fracturable LUTs. tecture explorations. Section 6 concludes. 3. A NEW COMPLEX BLOCK ARCHITEC- 2. BACKGROUND AND TERMINOLOGY TURE DESCRIPTION LANGUAGE The architecture of an FPGA consists of the set of blocks A key goal of this work is to enable architecture explo- that perform internal computing, the input/output blocks ration and CAD tool research for FPGAs with far more that communicate with the extra-chip environment, and the complex logic and interconnect than has been possible with programmable routing structure that connects them. As prior public tools.