Strathmore University SU+ @ Strathmore University Library Electronic Theses and Dissertations 2016 Analyzing error detection performance of checksums in embedded networks Mirza, A. N. Faculty of Information Technology (FIT) Strathmore University Follow this and additional works at: https://su-plus.strathmore.edu/handle/11071/2474 Recommended Citation Mirza, A. N. (2016). Analyzing error detection performance of checksums in embedded networks (Thesis). Strathmore University. Retrieved from http://su-plus.strathmore.edu/handle/11071/4844 This Thesis - Open Access is brought to you for free and open access by DSpace @Strathmore University. It has been accepted for inclusion in Electronic Theses and Dissertations by an authorized administrator of DSpace @Strathmore University. For more information, please contact [email protected] Analyzing Error Detection Performance of Checksums in Embedded Networks Ali Naqi Mirza Submitted in partial fulfillment of the requirements for the Degree of Master of Science in Computer Based Information Systems at Strathmore University Faculty of Information Technology Strathmore University Nairobi, Kenya June, 2016 This Thesis is available for Library use on the understanding that it is copyright material and that no quotation from the thesis may be published without proper acknowledgement Declaration I declare that this work has not been previously submitted and approved for the award of a degree by this or any other University. To the best of my knowledge and belief, the thesis contains no material previously published or written by another person except where due reference is made in the thesis itself. © No part of this thesis may be reproduced without the permission of the author and Strathmore University …..Ali Naqi Mirza…………………………………….. [Name of Candidate] ………………………………………………………… [Signature] ….June 7, 2016………………………………………... [Date] Approval The thesis of Ali Naqi Mirza was reviewed and approved by the following: Dr. Vitalis Ozianyi, PhD Faculty of Information Technology Strathmore University Dr. Joseph Orero, PhD Dean, Faculty of Information Technology Strathmore University Professor Ruth Kiraka Dean, School of Graduate Studies ii Abstract Networks are required to transport data from one device to another with adequate precision. For a majority of applications a system is expected to ensure that received data and transmitted data is uniform and consistent. Many elements can change one or more bits of a message sent. Applications therefore need a procedure for the purpose of identification and correction of errors during transmission. Checksums are frequently used by embedded networks for the purpose of identifying errors in data transmission. But decisions regarding which checksum to utilize for error detection in embedded networks are hard to make, since there is an absence of statistics and knowledge about the comparative usefulness of choices available. The aim of this research was to analyze the error detection performance of these checksums frequently utilized: XOR, one‟s complement addition, two‟s complement addition, Adler checksum, Fletcher checksum, and Cyclic Redundancy Check (CRC) and to assess the error detection effectiveness of checksums for those networks which are prepared to give up error detection efficiency in order to curtail costs regarding calculations and computations, for those wanting uniformity between error identification and costs, and finally for those networks which are ready to yield elevated costs for notably enhanced error detection. Even though there is no one size fits all method available, this research gives recommendations in order to decide as to which checksum approach to adopt. A bit flip fault design with manufactured error simulations was utilized for this research. Mathematical technique used for the proposed fault design was Monte Carlo simulations using Mersenne twister random number generator. This study concludes that the error identification performance of XOR, and Adler checksums for arbitrary and autonomous bit and burst errors is below an accepted level, rather 1‟s and 2‟s complement checksums should be utilized for networks prepared to surrender error identification efficiency in order to minimize the cost of calculations. Fletcher checksum should be utilized by networks wanting symmetry between computational costs and error identification and CRCs by networks prepared to yield greater costs of computation for notably enhanced error identification. iii Table of Contents Declaration ................................................................................................................................ ii Abstract .................................................................................................................................... iii Acknowledgements ................................................................................................................. vii Abbreviations and Acronyms ................................................................................................. viii Definition of Terms ................................................................................................................... ix List of Figures ............................................................................................................................ x List of Equations ....................................................................................................................... xi List of Tables .......................................................................................................................... xii Dedication .............................................................................................................................. xiii Chapter 1: Introduction .............................................................................................................. 1 1.1 Background ................................................................................................................. 1 1.2 Problem Statement ...................................................................................................... 3 1.3 Research Objectives .................................................................................................... 4 1.4 Research Questions ..................................................................................................... 4 1.5 Scope and Limitations ................................................................................................. 4 Chapter 2: Literature Review ..................................................................................................... 5 2.1 Introduction ................................................................................................................. 5 2.2 Embedded Networks ................................................................................................... 5 2.2.1 Restrictions Enforced by Host. ............................................................................ 6 2.2.2 Restrictions Enforced by Applications. .............................................................. 7 2.3 Error Detection ............................................................................................................ 9 2.3.1 Types of Errors. .................................................................................................. 10 2.4 Checksums ................................................................................................................. 12 2.4.1 XOR Checksum. ................................................................................................ 14 2.4.2 One‟s Complement Checksum. .......................................................................... 17 2.4.3 Two‟s Complement Checksum. ......................................................................... 19 2.4.4 Fletcher Checksum. ............................................................................................ 21 2.4.5 Adler Checksum. ................................................................................................ 23 2.5 Cyclic Redundancy Check (CRC) ............................................................................. 25 2.5.1 Modulo 2 Arithmetic. ......................................................................................... 30 iv 2.5.2 Polynomials. ....................................................................................................... 33 Chapter 3: Design and Analysis ............................................................................................... 38 3.1 Introduction ............................................................................................................... 38 3.2 Design Parameters ..................................................................................................... 38 3.3 Prospective Analysis Considerations ........................................................................ 38 3.4 Analysis ..................................................................................................................... 39 3.5 Additional Design Concerns ..................................................................................... 42 3.5.1 Impact of Primary Implant Values. .................................................................... 42 3.5.2 Identification of Burst Errors. ............................................................................ 42 3.5.3 Detection of Modifications in Data Sequence. .................................................