
Carnegie Mellon Field Programmable Gate Array (FPGA) Design of Digital Circuits 2014 Srdjan Capkun Frank K. Gürkaynak http://www.syssec.ethz.ch/education/Digitaltechnik_14 1 Adapted from Digital Design and Computer Architecture, David Money Harris & Sarah L. Harris ©2007 Elsevier Carnegie Mellon What will we learn? ¢ What are programmable logic devices? ¢ We will use a Field Programmable Gate Array (FPGA) in the exercises, what is this FPGA? ¢ How does an FPGA work ¢ InformaDon about the FPGA board we will use 2 Carnegie Mellon Logic Arrays ¢ Programmable logic arrays (PLAs) § AND array followed by OR array § Perform combinaonal logic only § Fixed internal connecIons ¢ Field programmable gate arrays (FPGAs) § Array of configurable logic blocks (CLBs) § Perform combinaonal and sequenIal logic § Programmable internal connecIons 3 Carnegie Mellon Programming PLAs ¢ Show how the PLA can be configured to realize: § X = (A · B · C) + (A · B · C) § Y = A · B A B C Inputs OR ARRAY M ABC AND Implicants OR ABC ARRAY N ARRAY AB P Outputs AND ARRAY X Y 4 Carnegie Mellon PLAs: Dot NotaDon Inputs M AND Implicants OR ARRAY N ARRAY P Outputs A B C OR ARRAY ABC ABC AB AND ARRAY X Y 5 Carnegie Mellon FPGAs: Field Programmable Gate Arrays ¢ Composed of: § CLBs (Configurable Logic Blocks): perform logic § IOBs (Input/Output Buffers): interface with outside world § Programmable interconnecIon: connect CLBs and IOBs ¢ Some FPGAs include other building blocks such as: mulDpliers and RAMs 6 Carnegie Mellon Xilinx Spartan 3 FPGA SchemaDc 7 Carnegie Mellon CLBs: Configurable Logic Blocks ¢ Composed of: § LUTs (LookUp Tables): perform combinaonal logic § Flip-flops: perform sequenIal funcIons § MulIplexers: connect LUTs and flip-flops 8 Carnegie Mellon Xilinx Spartan CLB 9 Carnegie Mellon Xilinx Spartan CLB consists of ¢ 3 LUTs: § F-LUT (24 x 1-bit LUT) § G-LUT (24 x 1-bit LUT) § H-LUT (23 x 1-bit LUT) ¢ 2 registered outputs: § XQ § YQ ¢ 2 combinaonal outputs: § X § Y 10 Carnegie Mellon CLB Configuraon Example ¢ Show how the CLB can be configured to realize: § X = (A · B · C) + (A · B · C) § Y = A · B 11 Carnegie Mellon CLB Configuraon Example ¢ Show how the CLB can be configured to realize: § X = (A · B · C) + (A · B · C) § Y = A · B (A) (B) (C) (X) (A) (B) (Y) 0 G4 F4 F3 F2 F1 F G4 G3 G2 G1 G 0 G3 G X 0 0 0 0 X X 0 0 0 A G2 Y X 0 0 1 1 X X 0 1 0 B G1 X 0 1 0 0 X X 1 0 1 X 0 1 1 0 X X 1 1 0 X 1 0 0 0 0 F4 X 1 0 1 0 A F3 F X 1 1 0 1 B F2 X x 1 1 1 0 C F1 12 Carnegie Mellon FPGA Design Flow ¢ A CAD tool (such as Xilinx Project Navigator) is used to design and implement a digital system. ¢ The user enters the design using schemac entry or an HDL. ¢ Correct funconality is verified using simulaon ¢ A synthesis tool maps your descripDon onto the FPGA. ¢ The result is a biile that contains configures the CLBs and the connecons between them and the IOBs. ¢ The biile is downloaded to the FPGA 13 Carnegie Mellon The FPGA board for the LAB Exercises ¢ Each lab group will have its own FPGA board for the exercises. 14 Carnegie Mellon What exactly is this FPGA board? ¢ Contains a Programmable Logic Device (FPGA) ¢ Various Interfaces § Switches and Lights § Video (VGA) Interface § Keyboard/Mouse Interface ¢ Support Circuits § Circuits to store the configuraon § Power and Clock for all the components 15 Carnegie Mellon What will we do with the FPGA Board ? ¢ At the end of the exercises, we will have built a 32-bit microprocessor running on the FPGA board. § It will be a small processor, but it will be able to execute small programs. ¢ Each week we will have a new exercise. § Not all exercises will require the board. ¢ You are encouraged to experiment with the board on your own. § It is not possible to destroy the board by programming! 16 .
Details
-
File Typepdf
-
Upload Time-
-
Content LanguagesEnglish
-
Upload UserAnonymous/Not logged-in
-
File Pages16 Page
-
File Size-