W&M ScholarWorks Dissertations, Theses, and Masters Projects Theses, Dissertations, & Master Projects 2003 Power considerations for memory-related microarchitecture designs Zhichun Zhu College of William & Mary - Arts & Sciences Follow this and additional works at: https://scholarworks.wm.edu/etd Part of the Computer Sciences Commons Recommended Citation Zhu, Zhichun, "Power considerations for memory-related microarchitecture designs" (2003). Dissertations, Theses, and Masters Projects. Paper 1539623427. https://dx.doi.org/doi:10.21220/s2-az56-s960 This Dissertation is brought to you for free and open access by the Theses, Dissertations, & Master Projects at W&M ScholarWorks. It has been accepted for inclusion in Dissertations, Theses, and Masters Projects by an authorized administrator of W&M ScholarWorks. For more information, please contact [email protected]. Power Considerations for Memory-related Microarchitecture Designs A Dissertation Presented to The Faculty of the Department of Computer Science The College of William Mary in Virginia In Partial Fulfillment Of the Requirements for the Degree of Doctor of Philosophy by Zhichun Zhu 2003 Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. APPROVAL SHEET This dissertation is submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy '/ Zhichun Zhu Approved, July 2003 daodong Zhang Thesis Advisor . Phil Kearns Brucp'TiOwekamp Dimitrios Nikolopoulos TH11 ,L ' </-5Vv£U-v Robert Noonan ) U -v v - Jun Yang University of California, Riverside Reproduced with permission of the copyright owner. Further reproduction prohibited without permission Table of Contents Acknowledgments vii List of Tables viii List of Figures x Abstract xiii 1 Introduction 2 1.1 Importance of Low-power Architecture D esigns .................................................. 3 1.2 Our W o rk ..................................................................................................................... 4 2 Background 8 2.1 Sources of Power Consumption .............................................................................. 8 2.2 Low-power Techniques .............................................................................................. 9 2.2.1 Power-saving Techniques at Physical, Circuit and Logic Levels . 10 2.2.2 Power-saving Techniques at Architectural Level .................................... 11 2.2.3 Power-saving Techniques at Software L ev el .......................................... 12 iii Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 3 Evaluation Environment 15 3.1 Evaluation M e tric s ..................................................................................................... 15 3.1.1 Performance M e tric s ..................................................................................... 15 3.1.2 Power and Energy Metrics ........................................................................... 16 3.1.3 Energy-efficiency Metrics ........................................................................... 17 3.2 Performance Evaluation T o o ls ................................................................................. 18 3.3 Energy Consumption Evaluation T o o ls ................................................................. 21 3.4 W orkloads ..................................................................................................................... 22 4 Access Mode Predictions for Low-power Cache Design 25 4.1 Significance of Low-power Cache D e s ig n .............................................................. 25 4.2 Related W o rk .............................................................................................................. 27 4.3 Comparisons between Phased and Way-prediction C aches ............................. 28 4.4 AMP Caches.............................................................................................................. 31 4.4.1 S tra te g y ............................................................................................................ 31 4.4.2 Power Consumption ..................................................................................... 33 4.5 Access Mode P re d ic to rs ........................................................................................... 34 4.5.1 D e s ig n s ............................................................................................................ 34 4.5.2 Accuracy ........................................................................................................ 37 4.5.3 Overhead ........................................................................................................ 38 4.6 Multicolumn-based Way-prediction ....................................................................... 39 4.6.1 Limitation of MRU-based Way-prediction .............................................. 39 4.6.2 Multicolumn Cache ..................................................................................... 42 iv Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 4.6.3 Power Considerations for Multicolumn C ache ....................................... 45 4.7 Experimental Environment .................................................................................... 49 4.8 Experimental Results ................................................................................................. 50 4.8.1 Comparisons of Multicolumn and MRU Caches .................................... 50 4.8.2 Energy Reduction of AMP Caches ........................................................... 53 4.8.3 Energy-efficiency of AMP Caches .............................................................. 59 4.9 S u m m a ry ..................................................................................................................... 62 5 Look-ahead Adaptation Techniques to Reduce Processor Power Consump­ tion 64 5.1 Motivation ................................................................................................................. 64 5.2 Load Indicator Schem e .............................................................................................. 68 5.2.1 Power Saving Opportunity ........................................................................ 68 5.2.2 Load In d ic a to r ............................................................................................... 70 5.3 Considerations for Load Indicator Scheme .......................................................... 75 5.4 Experimental Environment .................................................................................... 78 5.4.1 Power Savings ............................................................................................... 80 5.5 Effectiveness of Load Indicator Scheme ................................................................. 82 5.6 Combining Local and Look-ahead Optimizations ............................................. 85 5.6.1 Motivation ..................................................................................................... 85 5.6.2 Load-instruction Indicator ........................................................................... 88 5.7 Comparisons between Different Schemes .............................................................. 90 5.7.1 Power Savings ............................................................................................... 90 v Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. 5.7.2 Performance Im pact ...................................................................................... 92 5.7.3 Energy Reduction ......................................................................................... 93 5.7.4 Different Configurations ............................................................................... 94 5.7.5 Average Intervals in Each Power M ode ...................................................... 96 5.8 Load-register Indicator Schem e ................................................................................ 97 5.9 Effectiveness of Load-register Scheme ...................................................................... 100 5.9.1 Power Savings ................................................................................................ 100 5.9.2 Energy S avings ................................................................................................ 102 5.10 Related W ork ............................................................................................................... 103 5.11 S u m m a ry ...................................................................................................................... 105 6 Conclusion and Future Work 107 6.1 Conclusion .................................................................................................................. 107 6.2 Future Work ............................................................................................................... 109 Bibliography 112 vi Reproduced with permission of the copyright owner. Further reproduction prohibited without permission. ACKNOWLEDGMENTS Pursuing this degree is a long journey for me. I have learned a lot during this journey, not only from the study, the research work, but also from many people including my adviser, my professors, and my fellow students. I would like to thank all of them for their help. First