UC San Diego UC San Diego Electronic Theses and Dissertations Title Templates and Patterns : Augmenting High-Level Synthesis for Domain-Specific Computing Permalink https://escholarship.org/uc/item/69c8p7bj Author Matai, Janarbek Publication Date 2015 Peer reviewed|Thesis/dissertation eScholarship.org Powered by the California Digital Library University of California UNIVERSITY OF CALIFORNIA, SAN DIEGO Templates and Patterns: Augmenting High-Level Synthesis for Domain-Specific Computing A dissertation submitted in partial satisfaction of the requirements for the degree of Doctor of Philosophy in Computer Science by Janarbek Matai Committee in charge: Ryan Kastner, Chair Rajesh Gupta Ali Irturk Bhaskar D. Rao Michael B. Taylor 2015 Copyright Janarbek Matai, 2015 All rights reserved. The Dissertation of Janarbek Matai is approved and is acceptable in quality and form for publication on microfilm and electronically: Chair University of California, San Diego 2015 iii DEDICATION To mom and dad. iv EPIGRAPH I wanted a perfect ending. Now I’ve learned, the hard way, that some poems don’t rhyme, and some stories don’t have a clear beginning, middle, and end. Life is about not knowing, having to change, taking the moment and making the best of it, without knowing what’s going to happen next. Gilda Radner v TABLE OF CONTENTS Signature Page . iii Dedication . iv Epigraph . v Table of Contents . vi List of Figures . ix List of Tables . xv Acknowledgements . xvi Vita................................................................. xviii Abstract of the Dissertation . xx Introduction . 1 Chapter 1 Background . 7 1.1 Introduction . 7 1.2 High-Level Synthesis . 9 1.2.1 Scheduling . 10 1.3 Design with HLS . 15 1.3.1 Vivado High-Level Synthesis . 15 1.4 HLS Hello World . 18 1.5 Conclusion . 20 Chapter 2 Wireless Digital Channel Emulator . 22 2.1 Introduction . 22 2.2 Wireless Channel Model . 26 2.3 Hardware Design and Optimization . 29 2.3.1 Architecture . 29 2.3.2 Baseline . 30 2.3.3 Code Restructuring . 33 2.3.4 Bit-Width Optimization . 36 2.3.5 Pipelining/Unrolling/Partitioning (PUP) . 37 2.4 Results . 38 2.4.1 Verification/Integration . 38 2.5 Experimental Results . 40 2.6 Discussion . 44 vi 2.7 Related Work . 45 2.8 Conclusion . 47 Chapter 3 A Complete Face Recognition System . 50 3.1 Introduction . 50 3.2 Face Recognition subsystem . 52 3.2.1 Architecture of the Face Recognition Subsystem . 53 3.2.2 FPGA Implementation . 55 3.3 Experimental Results . 59 3.4 Implementation of the Complete Face Recognition System . 60 3.5 Conclusion . 63 Chapter 4 Canonical Huffman Encoding . 64 4.1 Introduction . 64 4.2 Canonical Huffman Encoding (CHE) . 66 4.3 Hardware Implementations. 69 4.3.1 Radix Sort . 72 4.3.2 Huffman Tree Creation . 74 4.3.3 Parallel Bit Lengths Calculation . 75 4.3.4 Canonization . 76 4.3.5 Codeword Creation . 77 4.4 Software Implementations . 79 4.5 Experimental Results . 80 4.5.1 Software Implementations . 80 4.5.2 Hardware Implementations . 82 4.5.3 Hardware and Software Comparison . 85 4.6 Related Work . 87 4.7 Conclusion . 88 Chapter 5 Restructured HLS Code . 90 5.1 Introduction . 90 5.2 Restructured Code . 93 5.2.1 Prefix sum . 94 5.2.2 Histogram . 99 5.2.3 SpMV: Sparse Matrix Vector Multiplication . 105 5.2.4 FFT . 112 5.2.5 Huffman Tree Creation . 116 5.2.6 Matrix multiplication . 123 5.2.7 Convolution. 127 5.2.8 Face Detection . 131 5.3 HLS User Study . 139 5.3.1 User Study-1 . 139 5.3.2 User Study-2 . 143 vii 5.4 Challenges . 147 5.4.1 Restructured Code Generation: Instruction level . 148 5.4.2 Restructured Code Generation: Task level . 148 5.4.3 Complex Application Design . 150 5.5 Conclusion . 151 Chapter 6 Composable, Parameterizable Templates for High-Level Synthesis . 153 6.1 Introduction . ..