Jpn. J. Appl. Phys. Vol. 38 (1999) pp. L 1015–L 1017 Part 2, No. 9A/B, 15 September 1999 c 1999 Publication Board, Japanese Journal of Applied Physics A New N-Channel Junction Field-Effect Transistor Embedded in the i Layer of a Pin Diode Hideharu MATSUURA, Kenji AKATANI, Michihisa UEDA, Kazushige SEGAWA, Hidemasa TOMOZAWA1, Katsuhiko NISHIDA1 and Kazuo TANIGUCHI2 Department of Electronics, Osaka Electro-Communication University, 18-8 Hatsu-cho, Neyagawa, Osaka 572-8530, Japan 1Eniwa Research and Development Center, Kyoto Semiconductor Corporation, 385-31 Toiso, Eniwa, Hokkaido 061-1405, Japan 2Department of Materials Science, Osaka Electro-Communication University, 18-8 Hatsu-cho, Neyagawa, Osaka 572-8530, Japan (Received June 9, 1999; accepted for publication July 12, 1999) We experimentally confirmed a basic operation of the n-channel junction field-effect transistor (JFET) embedded in the i layer (n¡ substrate) of a pin diode for X-ray detectors, which was proposed in Jpn. J. Appl. Phys. 37 (1998) L115. To electrically isolate the n-channel from the n¡ substrate, a pC ring is formed around the JFET and is reverse-biased, instead of a deep p layer under the n-channel (i.e., the conventional structure). In the proposed structure, only one type of donor is ion-implanted in the n-channel, while in the conventional structure, both donor and acceptor are ion-implanted there. For the first time, the role of the pC ring in the electrical characteristics of the n-channel JFET is experimentally elucidated. KEYWORDS: JFET, n-channel, new structure, front-end preamplifier for X-ray detectors, SDD, JFET embedded in pin diode gate of a four-terminal JFET which has a front gate and a 1. Introduction bottom gate. Silicon drift detectors (SDDs) enable the realization of In this letter, we experimentally investigate the role of the large-area X-ray detectors with spectroscopic energy reso- reverse-biased pC ring in determining the electrical character- lution.1,2) Since X-ray detectors are very sensitive to noise, istics of the n-channel JFET. we should avoid placing a long wire between a pin diode for an X-ray detector (X-ray pin diode) and a front-end junction 2. Experimental field-effect transistor (JFET). For this reason, it is necessary To form an n-channel in an n¡ substrate of Si with a donor to embed a JFET in the substrate (i layer) of the X-ray pin density of 2 £ 1012 cm¡3, phosphorus (P) of 2 £ 1010 cm¡2 diode. or 8 £ 1010 cm¡2 was ion-implanted with 500 keV. The peak To take advantage of the electron mobility, which is much position of the P distribution in Si was calculated to be about higher than the hole mobility, we should select an n-channel 0:8¹m from the surface, and the peak densities for the two JFET as well as a high-resistivity n-type substrate (n¡ sub- types of doses were calculated to be about 5 £ 1014 cm¡3 and strate). 2 £ 1015 cm¡3, respectively. The schematic cross section of the proposed SDD is shown Two 0:2-¹m-thick nC layers (source and drain) were in Fig. 1, and the top view around the center is shown in Fig. 2. formed by the thermal diffusion of P. Then, two 0:15-¹m- To reduce the capacitance of the X-ray pin diode, the area of thick pC layers (gate and ring) were formed by the thermal the nC layer (anode)3) is reduced. To form the depletion re- diffusion of boron (B). gion over the whole n¡ substrate, a high reverse-bias voltage Each size of JFET is shown in Fig. 3. The gate length C 3) (Vc) is applied to the p layer (cathode) of the X-ray pin and width were 8¹m and 144¹m, respectively. The electrical diode. To effectively collect electrons produced by X-rays measurement was carried out using three Keithley 236 Source at the anode, several pC rings are formed at the surface and Measure Units. are reverse-biased. For example, ¡20 V and ¡100 V are ap- plied to the innermost and outermost pC rings, respectively, at 3. Results and Discussion C Vc D¡100 V. Figure 4 shows the influence of the p ring voltage (Vring) ¡ To fabricate an n-channel JFET in the n substrate, a deep p as well as the gate voltage (VG) on the drain current (ID)at 4,5) region and a shallow n-channel region are usually formed. the drain-source voltage (VDS) of 4 V for the dose of 8 £ This is because the deep p region isolates the n-channel from 1010 cm¡2. In the figure, the solid and broken lines represent ¡ the n substrate electrically. In this conventional structure, the ID ¡ Vring characteristics at VG D 0 V and the ID ¡ VG however, ionized donors as well as ionized acceptors exist characteristics at Vring D 0 V, respectively. in the n-channel, suggesting that a lot of dopants generate First, we discuss the electrical isolation of the n-channel noise6) and reduce the electron mobility in the n-channel at from the n¡ substrate due to the reverse-biased pC ring. As a low operating temperature. is clear from the solid line, Vring influenced ID, indicating that Instead of the deep p region under the n-channel, we have the pC ring affects the n-channel depth. As a result, the pC proposed a new structure of an n-channel JFET with a pC ring ring behaves exactly like a bottom gate of the four-terminal around the JFET,7) which is shown in Figs. 1–3. The proposed JFET, as proposed in our previous paper.7) From the stand- C JFET is located in the innermost p ring, as shown in Figs. 1 point of the ID ¡ Vring characteristics, therefore, the n-channel and 2. Because the donor density of the n¡ substrate is rather is electrically isolated from the n¡ substrate when the pC ring low (about 2 £ 1012 cm¡3), the depletion region formed by is reverse-biased. C the reverse-biased p ring spreads over the bottom of the n- The value of ID decreased with VG from ¡3Vto¡17 V ¡ channel. This is why it separates the n-channel from the n more slowly than it did with Vring. This suggests that at C C substrate electrically. As a result, the p ring acts as a bottom Vring D 0 V, the depletion region formed by the p ring L 1015 L 1016 Jpn. J. Appl. Phys. Vol. 38 (1999) Pt. 2, No. 9A/B H. MATSUURA et al. Fig. 1. Schematic cross section of the X-ray pin diode with the proposed n-channel JFET. VG [V] -20 -15 -10 -5 0 P:500keV,8x1010 cm-2 V =4V 10 DS A] µ [ D I 5 :VG=0V :Vring=0V Fig. 2. Schematic top view around the center with the proposed n-channel 0 JFET. -20 -15 -10 -5 0 Vring [V] C Fig. 4. Dependence of ID on the reverse bias of the p ring (solid line) or the gate (broken line) at VDS D 4V. Figure 5 shows the ID ¡ VDS characteristics for 11 VG at Vring D¡20 V. According to the simulation, the deple- tion region in the n¡ substrate spreads over about 100¹m at Vring D¡20 V. As is clear from the figure, the typical ID ¡ VDS characteristics were obtained, and the saturation of ID appeared clearly, indicating that the pinch-off occurred. Therefore, from the viewpoint of the ID ¡ VDS characteristics ¡ also, we have experimentally demonstrated that the reverse- Fig. 3. Schematic cross section of the proposed n-channel JFET in the n C ¡ substrate. biased p ring can separate the n-channel from the n sub- strate electrically. The electrical characteristics of the JFET for the dose of 10 ¡2 does not spread over the entire bottom area of the n-channel. 2 £ 10 cm were also measured. The pinch-off Vring for Since the electronic built-in barrier between the n-channel and the dose of 2 £ 1010 cm¡2 was about ¡7 V, while the pinch- ¡ 10 ¡2 the n substrate is low, ID consists of two types of currents off Vring for the dose of 8 £ 10 cm was less than ¡20 V. ¡ through the n-channel as well as the n substrate just under Under the conditions of VDS D 4V,VG D 0 V and Vring D the n-channel. 0V,ID was in the linear region, and the values of ID were 10 ¡2 10 On the other hand, at VG < ¡17 V, ID increased due to the 2:6¹A and 11:4¹A for the doses of 2£10 cm and 8£10 ¡2 reverse-bias current between the gate and the drain. This is cm , respectively. The ratio of the latter ID to the former ID because at VG < ¡17 V, the gate current (IG) flowed and IG was 4:4. This ratio is reasonable because in the linear region, 8) was the same as ID. ID is proportional to the donor density in the n-channel. Jpn. J. Appl. Phys. Vol. 38 (1999) Pt. 2, No. 9A/B H. MATSUURA et al. L 1017 current JFET. Since the input voltage (Vin) is around 0 V in 10 -2 0.15 P: 500keV,8x10 cm VG [V] the operating condition, the output voltage (Vout) is around Vring= -20 V 0 half of the supplied voltage (VCC).