ADAPTIVE TRANSLINEAR ANALOG SIGNAL PROCESSING A PROSPECTUS Eric J. McDonald, Koji Mensa Odame, and Bradley A. Minch School of Electrical and Computer Engineering Cornell University Ithaca, NY 14853-5401 [email protected] ABSTRACT are directly implementable as networks of MITES. We have devised a systematic method of transforming high- One common implementation of a MITE unit is shown level time-domain descriptions of linear and nonlinear adap- in Fig. 1. In this case, we operate a floating-gate PMOS tive signal-processing algorithms into compact, continuous- transistor in weak-inversion in addition to using a cascode time analog circuitry using basic units called multiple-input transistor to reduce the effects of the gate-to-drain capac- translinear elements (MITES). In this paper, we describe itance and channel-length modulation. The input voltages, the current state of the an and illustrate the method with an VI and V,, capacitively couple into the floating gate through unit-sized capacitors. The drain current of this device is example of an analog phase-locked loop (PLL). given by I = Isew(I’,+1’d/UT, 1. CIRCUIT SYNTHESIS METHODOLOGY where I, is a pre-exponential scaling current, w is the weight- The class of dyiamic translinear circuits [ 1-31 makes possi- ing cwfficient of the inputs (accounting for the body-effect 2.’ _.ble a promising approach to the structured design of analog and the capacitive voltage divider, Cunjt/Ctota,),and UT is ”. .‘ signal and information processing systems [4]. Such cir- the thermal voltage, kT/q. ’ cuits are capable of accurately realizing a wide range of lin- ear and nonlinear systems whose behavior can be described 2. PHASE-LOCKED LOOP implicitly as a system of coupled static polynomial con- straints and algebraic diferenrial equntioris (ADEs) with We illustrate the synthesis methodology with an analog phase- time as the independent variable. The synthesis process be- locked loop as shown in Fig. 2. The phase detector can be gins with the decomposition of the high-level time-domain realized by a simple multiplier resulting in a low-frequency description into first-order ADEs. Afterwards, the dimen- component representing the frequency difference between sionless variables are replaced by ratios of signal currents the input and the voltage-controlled oscillator’s (VCO) out- to a unit current (whose values are forced to be positive by put. There will also be a high-frequency component (at adding offsets or using a differential representation). The approximately twice the input’s frequency) that will he re- system is then decomposed into translinear loop (TL) equa- moved by the loop filter. A first-order low-pass filter is suffi- tions and Kirchhoff‘s current law (KCL) equations which cient to accomplish this filtering operation [SI.By introduc- ing variable gain into the low-pass filter, we can combine both the loop filter and amplifier into a single circuit. The VCO can be realized by a quadrature oscillator. SignalInput DetectorPhase FilterLoop HAmplifier Output T vco Figure 1 : Implementation of MITE unit. Figure 2: Phase-locked loop block diagram, 0-7 803-8 104- l/03/$17.00 02003 IEEE 922 Figure 3: (a) Multiplier circuit. (h) First-order low-pass filter. 3. MULTIPLIER 4. LOW-PASS FILTER This section describes the process by which we transform The low-pass filter shown in Fig. 3(b) is discussedin several the polynomial constraint for a multiplier, papers (most completely covered in [3]) and therefore, will not he discussed in detail. It is worthwhile to mention that = xy, 2 the filter's behavior can he described by into the necessary translinear loops. The dimensionless vari- - ables are replaced with ratios of signal currents 10 a unit T- - GI, - I,, current. dt where the comer frequency (117) and gain (G)can he tuned by I, and GI, respectively. Since both the inputs and output need to represent positive and negative values, we must introduce offsets to force the 5. VOLTAGE-CONTROLLED OSCILLATOR variables to he strictly positive. The VCO's dynamics are considerably more complicated than the multiplier and filter. We begin by listing the con- Defining new currents to represent the shifted currents, straints for a quadrature oscillator (constant radius vector, r, and frequency, d$/dt), dr d0 T- = yr(p - r) T- = 1 (1) . dt dt ' where pis the desired radius and y determines the circuit's sensitivity to deviations in the desired radius. Moving these constraints to the Cartesian system results in x = r cos (0) y = r sin (8). (2) which can he represented by a translinear loop and a KCL Finding dxldt gives equation. dx dr d0 -= cos (0) - - T sin (0) -. dt dt dt Using MITE network synthesis techniques [3,6], we Using Eqs. 1 and 2 to eliminate 0 from the right-hand side can constmct a circuit to generate the output current, I,, results in dx Y r- = -x (p - r) - T as shown in Fig. 3(a). dt r E. 923 Similarly, we can calulate dyldt as giving us the following system description. dx dy T= 7- = -y+^/(p-r) r- =z+y(p-r) IC# 1 dt dt 4 Beginning with the radius calculation, we can square both sides and introduce offsets to provide strictly positive currents (note that T does not need an offset as it will always 0’. he positive) and then expand the right-hand side. TZ = 2 + y2 = (a - j)2 + (b- j)2 Figure 4 Inverting output structure used to introduce a T’ = a2+ b2+ 2j2 - Zj(a b) + + dlldt. Introducing current ratios and solving for I,. (as well as defining I2f ZIf), we find that every I1 cancels out and the result simplifies to this relationship and solving for the capacitor current results in the following TL and KCL equations 1,” = 1,” + 1; + IzfIf - I2f (Ia + Ib) I IbIr I IT IvIp+ $& + IfIpIv IfI& co - Dividing both sides by I, allows us to reduce the above to I, I, 4 I1 I, 4 LIl five TL equations and one KCL equation. vv---- Iaz Id Ia3 Io 5 106 I - 1,’ + IZfIf I2fIa IZfIb - - where we define as 71,. An almost identical procedure I- I, I, I, I, I, ww-v- will produce the equations defining the capacitor current for Ir1 172 173 174 175 the ‘h’ side. Following the same circuit construction techniques, these equations can be implemented with a circuit comprising I1 MITEs (not shown). A similar approach may be used to decompose the re- maining equations. Beginning with the original expression, If one were to make a separate MITE network to gener- ate each of the 12 temporary currents listed above (10[-06, Ibl-bG), it would require a total of 44 MITEs plus some ad- ditional mirroring circuitry. However, our synthesis method- we add offsets to x and y. introduce current ratios, and rear- ology allows for efficient sharing of redundant circuitry. There range to find are obvious reductions when currents are identical as in the case of Ia3 and Ib3 as well as Ia4 and IM.The more inter- esting opportunities arise when products share many of the same currents. For instance, IaSand I-6 differ by only one current. The voltages within the circuit are representative of (We chose to leave 7 as a dimensionless scaling factor that will later be combined with a DC current.) We can remove log-compressed products of currents. Thus, for Ia5 and IaG. the rdI,/dt expression through the introduction of an in- if we have a voltage that represents verting output structure shown in Fig. 4 where the output current is related to the capacitor current by dIa IJca 7- = _- we could use it as an input to two separate MITEs to gen- dt IT ’ erate I,, and Io~if each MITE’S other control gate voltage where I,, is the capacitor current and I, is a function of represented log (Ip) and log (I7)respectively as shown in the value of the capacitor, T, the thermal voltage, and the Fig. 5. The sharing of circuitly is similar lo the way one weighting of the MITE inputs (I, CUT/WT)[6]. Using factors out common expressions. This example is equiva- 924 Y) 1 Figure 5: Example of sharing a voltage, Vshare.that repre- sents a log-compressed product of currents. lent to factoring out IfITT/IaIlas follows. Figure 6 (a) Frequency control current of VCO. (b) Input and VCO output after locked. By sharing redundant circuitry, the original 44 MITES can 8. REFERENCES be reduced to 23. After the sharing of redundant circuitry, [l] J. Mulder, W. A. Serdijn, A. C. van der Woerd, the entire phase-locked loop, including the radius calcula- and A. H. M. van Roermund, “Dynamic tanslinear tion, low-pass filter, and multiplier, require a total of 42 circuits-an overview,” in Pmc. of the Second IEEE- MITES. CAS Region 8 Workshop on Analog and Mixed IC De- sign, Baveno, Italy, September 1997, pp. 65-72. 6. RESULTS [2] J. Mulder, W. A. Serdijn, A. C. van der Woerd, and A. H. M. van Roermund, mnamic Transliriear and We have fabricated a VCO, a variety of low-pass filters, and Log-Domairi Circirirs: Analysis and Synthesis, Kluwer, many static MITE networks in a OSpm double-poly CMOS Boston, 1999. process. With an on-chip capacitor of 750fE the VCO had a tunable frequency range of approximately lOOHz to 5OkHz. [3] B. A. Minch, “Synthesis of static and dynamic The low-pass filters demonstrated a wide range of tunable multiple-input translinear element networks,” Com- cut-off frequencies from a few Hz to 100’s of kHz.