Architecture HP 9000 V-Class Server Second Edition A3725-96022 HP 9000 V-Class Server Customer Order Number: A3725-90004 March, 1998 Printed in: USA Revision History Edition: First Document Number: A3725-96004 Remarks: Initial release October, 1997. Edition: Second Document Number: A3725-96022 Remarks: Released March, 1998. Notice Copyright Hewlett-Packard Company 1997. All Rights Reserved. Reproduction, adaptation, or translation without prior written permission is prohibited, except as allowed under the copyright laws. The information contained in this document is subject to change without notice. Hewlett-Packard makes no warranty of any kind with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. Hewlett-Packard shall not be liable for errors contained herein or for incidental or consequential damages in connection with the furnishing, performance or use of this material. Contents Preface . xiii New in Second Edition . xiii System platforms . xiii Notational conventions . xiv 1 Introduction . 1 The PA-8200 processor . .2 The node . .3 Control and status registers (CSRs) . .5 Description of functional blocks. .5 Exemplar processor agent controller . .5 Exemplar routing attachment controller—Hyperplane crossbar . .6 Exemplar memory access controller. .7 ECUB and core logic bus. .8 System configurations . .9 Shared memory . .10 2 Physical address space . 13 Physical addresses . .14 Coherent memory space . .17 Coherent memory layout . .18 Addressing a byte of memory. .20 Memory interleaving . .22 Memory interleave generation. .23 Ring (memory block) and bank index selection . .24 Memory block interleave pattern . .25 Memory bank interleave pattern . .26 Bank interleaved memory pattern . .27 Block and bank interleave memory pattern . .28 Core logic space . .30 Local I/O space . .31 Non-I/O CSR space . .32 CSR access . .33 Processor-local access . .33 EPAC-local access. .33 System accesses . .34 Access to nonexistent CSRs . .35 Table of Contents iii System Configuration register . 35 EPAC Configuration register . 37 EPAC Processor Configuration register. 38 EPAC Memory Board Configuration register . 39 EMAC Configuration register . 40 EMAC Memory Row Configuration register . 41 3 Caches. 43 Processor caches . 44 Cache coherence between processors . 46 Accelerated cache coherence. 46 Address aliasing . 48 Equivalent aliasing . 48 Nonequivalent aliasing. 48 Instruction aliasing. 49 4 Data mover. 51 Overview . 52 Message transfers . 52 Data copy . 52 Data mover features . 52 Data mover implementation . 54 Functional overview . 55 Input registers . 56 Message and copy state machine . 56 Operation status queues . 56 Messaging and data copy CSRs . 57 EPAC Operation Context registers. 57 EPAC Operation Address registers. 59 EPAC Input Command registers . 59 EPAC Source and Destination Physical Page Frame registers. 62 EPAC Source and Destination Offset registers . 63 EPAC Operation Status Queue registers . 64 EMAC Message Reception Area Configuration register . 67 EMAC Message Reception Area Offset registers. 68 EMAC Message Completion Queue Configuration register . 69 EMAC Message Completion Queue Offset registers . 70 EMAC Message Allocation address . 71 EMAC Message Completion Enqueue address . 72 EMAC Message Completion Dequeue address . 74 Memory structures . 76 Message Reception area . 76 Message Completion Queue area . 76 Block Translation Table definition . 78 iv Table of Contents 5 Synchronization . 81 Coherent semaphore instructions. .82 Noncoherent semaphore operators . .83 Barrier synchronization . .85 EPAC semaphore addresses . .86 EPAC Fetch Operation addresses . .86 EPAC Noncoherent Read and Write Operation addresses . .86 EPAC Coherent Increment addresses . .87 PA-8200 TLB Entry U-bit . .88 6 Interrupts . 89 Overview . .90 Processor interrupts . .91 Utilities board interrupts . .92 EPAC interrupt logic . .95 EPAC Interrupt Delivery registers . ..