Influence of the State of Polysilicon/Silicon Dioxide Interface on MOS Properties N. Lifhitz s. LWyi Bell Laboratories Murray Hill, New Jersey 07974 compared to that in the bulk of polysilicon which also contributes ABSTRACT to enhanced resistivity. We suggestthat thin a (5100 A) resistivesublayer of polysilicon near the oxideinterface can have a pronounced effect Thepresence of thisresistive sublayer would produce little on the MOScapacitance-voltage characteristics. On the depletion side of the curve the lower effective work-function difference C-V effect on such characteristics as sheet resistivity of the polysilicon. leadshigher ato threshold forstrong inversion. On the accumulation side the MOS capacitance is lowered due to the added On the other hand it should manifest itself through a degradation thickness of the depletion sublayer. With the help of the sublayer model we attempt to explain the of MOS C-V characteristics.Qualitatively, for n-poly gateand p- anomalousbehavior often observed in MOS capacitorswith silicide/polysilicon gates. The sublayer depletion activates traps due substrate,the effect is twofold.Firstly, the slope of C-V curves tothe heavyimpurities (Cu,Fe, and Ta)atthe interface, considerable amount of which were observed in these samples by becomesless steepand threshold Voltageof n-channeldevices is Auger spectroscopy. shiftedto higher voltages. Secondly, the MOS capacitancein the 1. INTRODUCTION flat-band to weak-accumulationregion of the C-V curve is lower It iswell knownthat MOS capacitance-voltagecurves and dueto the finitethickness of the resistivesublayer. The latter MOSFET thresholds are sensitive to the presence of various states effect is unobservable on the depletionside of thecurve and inoxide and at the silicon-oxideinterface [I].One is usually disappears in strong accumulation. concerned with the state of the Si/Si02 interface or withcharged The purpose of this work is to suggest a possible explanation to stateswithin the gateoxide but rarely with those on theouter the unusual behavior often observed in MOS devices containing a interface of the oxides. Of course,neglecting thelatter is well silicide-polysilicon gate structure with the metal silicide produced by justified when the layer immediately over the oxide is a metal or sputtering and sintering. They consistently exhibited degraded C-V highly doped polysilicon. characteristics after hightemperature sintering. We believe that The situation may be quite different when the doping profile in our model which postulates the existence of a resistive sublayer at a polysilicon gate is nonuniform.In particular,one may havea poly/Si02interface can account for all essentialfeatures of the verythin (-100 A) butresistive sublayer polysiliconof observedbehavior. From theobserved C-V curves we make an immediatelyadjacent to the gateoxide. Theexistence of sucha estimate of the requiredthickness of the resistivelayer to be of layer can be brought about by the very presence of the poly/oxide order 60 A, which is not unreasonable. Furthermore, our model is boundary which serves as a natural stop for the diffusion of certain indirectlysupported by Auger data [4] whichshowed largea deep level impurities, such as Cu and Fe. Moreover, in the vicinity concentration of heavy impurities at the poly/SiO2 interface. It is of the interface a greater percentage of donor impurities is inactive probable thatthese impurities (Cu andFe) segregate atthe interface during the sintering step. 3.4 54 - IEDM 82 CH1832-5/82/0000-0054$00.75 0 1982 IEEE theouter interface, viz. SiO2/poly,rather than that of theinner 11. EXPERIMENTAL oxide interface, that was responsible for the degradation of the CV Thermaloxide 4000 A thick was grown on Wacker ptype characteristics. <loo> orientedwafers. The wafers were implanted through the To confirm this hypothesis we took some of the samples which oxide with boron to achieve a carrier concentration of 4 . 10l6 cm-3 exhibited theafter-sintering characteristic (b)and etched the at the SiiOz interface. The oxide was subsequently etched away silicide away. Afterthis step the measured curves were still anda 250 A thickgate oxide was grown. A polysiliconlayer of identical to(b). However,after 15 minutes of phosphorus thickness 3500 A was then deposited and doped with phosphorus by diffusion at 9OO'C the MOS characteristics returned to their original diffusion from PBr3source. Tantalum silicide layer (2500 A) was undistortedshape, cf. curve(c) in Fig. 1. Inour view,this cosputteredonpolysilicon surface. The structure was then experiment gives a conclusive evidence of the importance of the patternedand reactive ion etched so asto form MOS capacitors outer interface since a brief diffusion step could not possibly affect with poly/silicide upper electrodes. the inner interface. After patterning, the samples were sintered at 900'C for 30 min in Ar atmosphere to form a stable low-resistivity TaSi2 [2]. It was 111. THE MODEL noticed thatafterthe hightemperature sintering, C-V Our model assumes that during the high temperature sintering characteristics underwent a drastic change. heavy impurities (e.g., Cu or Fe) which are present in the silicide A typical result is shown in Fig. 1. Before sintering the shape of or polysilicon diffuse in polysilicon towards the oxide and sink at theinterface, givingrise toa highdensity of surfacetraps of the curve (a) is similar to that usually obtained with polysilicon gate (withoutsilicide). After sintering the CV curves(b) behave in a acceptortype. On the other hand, the dopant concentration in manner similar to that usually attributed to the presence of a large polysiliconduring high temperature sintering is decreased dueto number of interface traps 13). This characteristic behavior includes diffusion of phosphorus into silicides. The compensation effect of adegraded and vneven slope as well asa washed out threshold the surface trapsbrings about the formation of ahighly resistive point. The unwelcome changes were clearly introduced during the layer in polysilicon. temperature sintering. Next we consider the band diagram of the gate structure, Fig. 2. Althoughthe C-Vcharacteristics shown in Fig. 1 (a,b)can Atequilibrium, Vo = 0, the siliconlayer under the oxide is in undoubtedly be explained in a conventional way, assuming interface depletion, Fig. 2a. The broken lines correspond to the presence of trapsand fixed oxide charges atthe Si/SiOZ interface,such an a depleted sublayer of polysilicon and solid lines show the case of a explanationwould necessarily involve numbera of crd hoc uniformly and heavily doped polysilicon. assumptions.In particular, one would have to postulate a special Consider now how our model explains the essential features of combination of interface traps and fixed oxide charges in order to the observed C-V characteristics.Firstly, we notethat the explain theobserved intersection of curvesa and b. Moreover, existence of the resistive layer lowers the built-in voltage between such a peculiar combination would appear unlikely to result from a the n-polysilicon gate and the psi substrate. This clearly increases short 900'C sintering step. We were, therefore, led to consider an the threshold voltage for strong inversion. In depletion at the same alternative explanation, based on the idea that it was the state of applied voltage, e.g., at Vr = 0, the electric field in the oxide is less 3.4 IEDM 82 - 55 than in the ideal case, cf. Fig. 2a. This leads to narrower depletion of the capacitor.However, during high temperature treatment region insilicon and hence higher capacitance. Qualitatively, this redistribution of phosphorusbetween poly andTaSi2 occurs. effect is similar to the usual case when the traps are on the Si/Si02 Furthermore, it is likely thatthe source of heavyimpurities is interface. As usual, charging and discharging of the fast traps leads containedwithin the Tail layer so thatduring the high- to a degraded slope of the C-V curve [31. temperature sintering the density of these impurities in polysilicon is increased due to diffusion from the source. Quite generally, the However, the crossing of the original and degradedcurves is effect of the heavyimpurities is compensatingas they trap and peculiar to our model.In weak accumulation(Fig. 2b) the depletethe mobilecharge. In Fig.3 we plotsheet resistance of a existence of a depleted sublayer results in lower capacitance. It is poly layer 4000 thick covered by a TaSil layer as a function of easy to show that this sublayer of thickness d gives rise to a relative A sinteringtemperature (30 min. in Ar). After each temperature change in the capacitance AC/C given by: cycle the silicidelayer was plasma-etchedand sheet resistance of -=--AC d Cox c do, e ' the poly layer measured. Original sheet resistance was 20 OD. It where do, is the oxidethickness (-250 A) and cox, c are, grew to 59 ODduring the 900'Csintering which is astandard respectively, the oxide and the polysilicon dielectric constants. The processstep. It is plausible thatthis change is associated with a maximum AC/C occurs at Vo = -1.4 v and equals = 7% which combination of depletion andcompensation of polysiliconaway givesd 60 A. Suchthickness of the resistivelayer seemsto us fromthe oxideinterface. As discussedabove these effects are notunreasonable. We can also estimate from Poisson's equation moresevere near the boundary. Under such conditions the the required density N- of fixed negative charge which accounts for detrimental effects of the contaminated interface come intoplay.