CS2 Supplementary Notes 2000-01 1 COMPUTER SYSTEMS. 1.1 Digital Computers. A digital computer is a programmable digital system possessing the following elements (may be present in multiplicity). 1. Memory Unit: used to store programs and operands (data); usually location addressable. 2. Execution Unit: consisting of at least an ALU, which performs all data processing functions (logical and arithmetic). 3. Control Unit: a synchronous stored program programmable controller. 4. I/O Unit: provides communication with other systems (and the outside world). The ALU and CU are in intimate communication: CU monitors condition codes, generates ALU function selects, and controls movement of data. The CU and ALU, together with possibly a few storage registers, are therefore often considered as a single entity called a central processing unit (CPU ). In the early 1970s, LSI technology (MOS) made it possible to fabricate an entire CPU (admittedly a rather small and simple one) on a single chip. An integrated CPU is called a microprocessing unit (MPU ) or simply a microprocessor . Whether the CPU is a single chip, or a board (e.g.in a minicomputer), or a number of boards, its connection to the rest of the machine is limited typically to one or two data buses (with associated address and control buses). Machines which have completely separate buses for instructions and operands are called Harvard architectures . An example is the first commercial microprocessor, the INTEL 4004 (in 1971), which had an 8-bit instruction bus and a 4-bit operand bus. Most machines, however, use only one bus to fetch instructions and read/write operands: this is the Princeton or von Neumann architecture . The width in bits (or lines) of the data bus is an important characteristic of the CPU. In the 1970s it was possible to classify machines in the following way: large machines (mainframes) typically had 32 CPU data bus lines; minicomputers (e.g. DEC PDP 11) typically had 16; and microcomputers (e.g. original IBM PC) typically 8. However, with VLSI, microprocessors with the performance and data bus width of minicomputers and small to medium mainframes are now in existence. The width of the address bus determines the maximum number of locations which can be addressed; the set of all possible locations constitutes the address space of the CPU. The address space can be very large even in microprocessors: e.g. the Pentium has a space of 2 32 bytes or 4G bytes (1M:=1K.1K; 1G:=1K.1M). Using standard memory SIMMs have only a capacity of 128M bytes, 4G bytes is 128 such SIMMs. This would be expensive even in a large system and usually there are large sections of unpopulated address space (no physical devices using addresses in these regions). The memory addressed via the CPU address bus (i.e. that in the Memory Units) is referred to as primary memory . Most installations have a much larger backing store or secondary memory which is treated as a subsidiary external system and is accessed via specialised I/O units called secondary storage controllers . The CPU can communicate not only with its primary memory, but also with its I/O units, which typically contain at least one or two registers addressable by it. Some CPUs have a separate address space for I/O devices. This can be done by inclusion of one extra line, say I/O enable, but special I/O instructions are needed also (e.g. Pentium family). Other CPUs simply use the memory address bus to place their I/O devices, which then appear like memory locations to the CPU. This is called memory mapped I/O (e.g. MC68000 family). 1.2 Bus Communications. We have seen how various computer subsystems are interfaced to a system address/data bus. Data transfer on a bus is a transaction involving one source subsystem, and, usually one destination. Each such transfer or bus cycle is conducted under the control of the subsystem which is currently driving the address and Page 1 control buses, the bus master for that cycle. We will consider only cycles of the type involving two subsystems: one bus master and a bus slave . Each bus master will, of course, be a subsystem with an internal controller, such as a CPU (and other devices like DMACs), which is capable of driving the address bus. In the simplest systems the only potential bus master is the (single) CPU. In more complex systems several subsystems may have the ability to be bus masters. If several masters wish to use a shared bus, it is necessary to arbitrate between them. This is often done by a separate subsystem called a bus arbiter , which each potential master can request for bus control. The arbiter grants the bus to one master at a time. There are several algorithms which can be used to decide which master will be issued with a grant: e.g masters can be prioritised. Also the arbiter may allow one master to hold the bus until it has finished its transfer, or it may allow each master only one cycle at a time before forcing rearbitration. Slaves are, by definition, addressable devices. The address bus defines a system address space (n-bit address bus gives 2 n word address space). Each slave appears in this space as one or more addressable locations (usually locations within a slave are contiguous). A slave may be a memory mapped I/O device with a couple of locations, or a large memory unit with millions. It is necessary for an address to specify not only which location within a slave is being addressed, but also which slave is involved. Each slave must be allocated a unique portion of the address space which it will occupy. The more significant bits of the address bus are usually used to select the the slave in question. Often these bits are interpreted by a single central address decoder which then sends an enable signal to the slave required. This —decoder“ is not usually as simple as the decoder circuit discussed earlier, since different slaves can occupy different amounts of address space. A memory unit may require tens of millions of addresses, any one of which will cause it to be enabled, while an I/O interface may have as few as one or two. Thus one output of the address decoder may need to go active for tens of millions of different inputs, while another responds to only one. In any case, at most one output should go active at any one time. Address Decoder Address bus (usually upper Selects to different lines) slaves: active select will enable slave Note that any master which cannot drive all address lines will be unable to access large areas of the address space. Note also, that a master in one cycle can sometimes be a slave in another. Subsystems which have master/slave capability must have I/O interfaces to the address and control buses as well as the data bus. When a bus master has control of the bus, it will activate the address bus, putting the address of the required location onto it. Various control lines are also necessary to manage the transfer. The master will usually need at least: 1) Read/Write Line (say H=read, L=write) which will indicate to the slave whether the master is going to read or write to it. 2) Address Valid (say L=address valid) indicates to all slaves when the value on the address bus is valid, to avoid ambiguities, when, for example the lines are in transition. The address decoder will usually be disabled (all outputs inactive) when the address valid is inactive. It cannot in general be assumed that the master knows how long the slave will need to identify its address, store data written to it, or present valid data requested from it. The problem is particularly acute with mass produced standard microprocessors, where a single type of device can be used in a myriad of different systems containing other subsystems of widely differing speeds. Several strategies are used to overcome this. Page 2 2 INSTRUCTIONS. Instructions fetched and executed by the CPU vary from machine to machine. The collection of instructions which a particular CPU can execute comprises its instruction set . Although instructions are fetched, via the data bus, in binary form or machine code , it is normal to associate with each a mnemonic which describes its function: but this, of course, is for human consumption only. An instruction may be several CPU words long, and so may involve more than one memory cycle to fetch. For example a 68000 instruction can be anything from 1 to 5 words long (each inst word must be stored in a 16-bit memory word). Instructions in general can be classified as: 1) Control Instructions. Normally CU executes instructions sequentially but it is sometimes desirable to alter this. Branch or jump instructions direct the CU to begin executing at some location specified by the instruction itself. Simple branches may be unconditional or may depend on status inputs from e.g. the ALU (i.e. condition codes). Most CPUs save the condition codes from the last instruction in a special internal register called the status register (or SR for short) (also condition code register (CCR for short)). Other branching instructions may call subroutines or govern more sophisticated looping behaviour. Additionally, many machines have control instructions which can e.g. stop the CPU and wait for some external event, reset the rest of the system etc. 2) Data Processing Instructions tell the CPU to operate on data.