Overview of Microprocessors Lecturer: Sri Parameswaran Notes by : Annie Guo 1 Lecture overview z Introduction to microprocessors z Instruction set architecture z Typical commercial microprocessors 2 Microprocessors z A microprocessor is a CPU on a single chip. z If a microprocessor, its associated support circuitry, memory and peripheral I/O components are implemented on a single chip, it is a microcontroller. z We use AVR microcontroller as the example in our course study 3 Microprocessor types z Microprocessors can be characterized based on z the word size z 8 bit, 16 bit, 32 bit, etc. processors z Instruction set structure z RISC (Reduced Instruction Set Computer), CISC (Complex Instruction Set Computer) z Functions z General purpose, special purpose such image processing, floating point calculations z And more … 4 Typical microprocessors z Most commonly used z 68K z Motorola z x86 z Intel z IA-64 z Intel z MIPS z Microprocessor without interlocked pipeline stages z ARM z Advanced RISC Machine z PowerPC z Apple-IBM-Motorola alliance z Atmel AVR z A brief summary will be given later 5 Microprocessor applications z A microprocessor application system can be abstracted in a three-level architecture z ISA is the interface between hardware and software FORTRAN 90 C program program FORTRAN 90 C program program compiled compiled to ISA program to ISA program Software ISA level Hardware ISA program executed by hardware Hardware 6 ISA z Stands for Instruction Set Architecture z Provides functional specifications for software programmers to use/program hardware to perform certain tasks z Provides the functional requirements for hardware designers so that their hardware design (called micro-architectures) can execute software programs. 7 What makes an ISA z ISA specifies all aspects of a computer architecture visible to a programmer z Basic z Instructions Instruction format Addressing modes z Native data types z Registers z Memory models z advanced z Interrupt handling 8 To be covered in the later lectures Instructions z This is the key part of an ISA z specifies the basic operations available to a programmer z Example: z Arithmetic instructions z Instruction set is machine oriented z Different machine, different instruction set z For example 68K has more comprehensive instruction set than ARM 9 Instructions (cont.) z Instruction set is machine oriented z Same operation, could be written differently in different machine z AVR Addition: add r2, r1 ;r2 Å r2+r1 Branching: breq 6 ;branch if equal condition is true Load: ldi r30, $F0 ;r30 Å Mem[F0] z 68K: Addition: add d1,d2 ;d2 Å d2+d1 Branching: breq 6 ;branch if equal condition is true Load: mov #1234, D3 ;d2 Å 1234 10 Instructions (cont.) z Instructions can be written in two languages z Machine language z made of binary digits z Used by machines z Assembly language z a textual representation of machine language z Easier to understand than machine language z Used by human beings 11 Machine code vs. assembly code z There is a one-to-one mapping between the machine code and assembly code z Example (Atmel AVR instruction): For increment register 16: z 1001010100000011 (machine code) z inc r16 (assembly language) z Assembly language also includes directives z Instructions to the assembler z Example: z .def temp = r16 12 z .include “mega64def.inc” Data types z The basic capability of using different classes of values. z Typical data types z Numbers z Integers of different lengths (8, 16, 32, 64 bits) Possibly signed or unsigned Commonly available z Floating point numbers, e.g. 32 bits (single precision) or 64 bits (double precision) Available in some processors such as PowerPC z BCD (binary coded decimal) numbers Available in some processors, such as 68K z Non-numeric z Boolean z Characters 13 Data types (cont.) z Different machines support different data types in hardware z e.g. Pentium II: Data Type 8 bits 16 bits 32 bits 64 bits 128 bits Signed integer 999 Unsigned integer 999 BCD integer 9 Floating point 99 z e.g. Atmel AVR: Data Type 8 bits 16 bits 32 bits 64 bits 128 bits Signed integer 9 Unsigned integer 9 BCD integer Floating point 14 Registers z Two types z General purpose z Special purpose z Used for special functions z e.g. Program Counter (PC) Status Register Stack pointer (SP) Input/Output Registers z Stack pointer and Input/Output Registers will be discussed in detail later. 15 General Purpose Registers z A set of registers in the machine z Used for storing temporary data/results z For example z In (68K) instruction add d3, d5, operands are stored in general registers d3 and d5, and the result are stored in d5. z Can be structured differently in different machines z For example z Separated general purpose registers for data and address 68K z Different numbers registers and different size of each registers 32 32-bit in MIPS 16 16 32-bit in ARM Program counter z Special register z For storing memory address of currently executed instruction z Can be of different size z E.g. 16 bit, 32 bit z Can be auto-incremented z By the instruction word size z Gives rise the name “counter” 17 Status register z Contains a number of bits with each bit associated with CPU operations z Typical status bits z V: Overflow z C: Carry z Z: Zero z N: Negative z Used for controlling program execution flow 18 Memory models z Data processed by CPU is usually large and cannot be held in the registers at the same time. z Both data and program code need to be stored in memory. z Memory model is related to how memory is used to store data z Issues z Addressable unit size z Address spaces z Endianness z Alignment 19 Addressable unit size z Memory has units, each of which has an address z Most common unit size is 8 bits (1 byte) z Modern processors have multiple-byte unit z For example: z 32-bit instruction memory in MIPs z 16-bit Instruction memory in AVR 20 Address spaces z The range of addresses a processor can access. z The address space can be one or more than one in a processor. For example z Princeton architecture or Von Neumann architecture A single linear address space for both instructions and data memory z Harvard architecture Separate address spaces for instructions and data memories 21 Address spaces (cont.) z Address space is not necessarily just for memories z E.g, all general purpose registers and I/O registers can be accessed through memory addresses in AVR z Address space is limited by the width of the address bus. z The bus width: the number of bits the address is represented 22 Endianness z Memory objects z Memory objects are basic entities that can be accessed as a function of the address and the length z E.g. bytes, words, longwords z For large objects (>byte), there are two ordering conventions z Little endian – little end (least significant byte) stored first (at lowest address) z Intel microprocessors (Pentium etc) z Big endian – big end stored first 23 z SPARC, Motorola microprocessors Endianness (cont.) z Most CPUs produced since ~1992 are “bi-endian” (support both) z some switchable at boot time z others at run time (i.e. can change dynamically) 24 Big Endian & Little Endian z Example: 0x12345678—a long word of 4 bytes. It is stored in the memory at address 0x00000100 Address data z big endian: 0x00000100 12 0x00000101 34 0x00000102 56 0x00000103 78 Address data z little endian: 0x00000100 78 0x00000101 56 0x00000102 34 0x00000103 12 25 Alignment z Often multiple bytes can be fetched from memory z Alignment specifies how the (beginning) address of a multiple-byte data is determined. z data must be aligned in some way. For example z 4-byte words starting at addresses 0,4,8, … z 8-byte words starting at addresses 0, 8, 16, … z Alignment makes memory data accessing more efficient 26 Example z A hardware design that has data fetched from memory every 4 bytes z Fetching an unaligned data (as shown) means to access memory twice. 27 Instruction format z Is a definition z how instructions are represented in binary code z Instructions typically consist of z Opcode (Operation Code) z defines the operation (e.g. addition) z Operands z what’s being operated on z Instructions typically have 0, 1, 2 or 3 operands 28 Instruction format examples OpCode OpCode Opd OpCode Opd1 Opd2 OpCode Opd1 Opd2 Opd3 29 Example (AVR instruction) z Subtraction with carry z Syntax: sbc Rd, Rr z Operation: Rd ← Rd –Rr –C z Rd: Destination register. 0 ≤ d ≤ 31 z Rr: Source register. 0 ≤ r ≤ 31, C: Carry z Instruction format 0 0 0 0 1 0 r d d d d d r r r r 15 0 z OpCode uses 6 bits (bit 9 to bit 15). z Two operands share the remaining 10 bits. 30 Instruction lengths z The number of bits an instruction has z For some machines – instructions all have the same length z E.g. MIPS machines z For other machines – instructions can have different lengths z E.g. M68K machine 31 Instruction encoding z Operation Encoding z 2n operations needs at least n bits z Operand Encoding z Depends on the addressing modes and access space. z For example: An operand in direct register addressing mode requires at most 3 bits if the the number of registers it can be stored is 8. z With a fixed instruction length, more encoding of operations means less available bits for encoding operands 32 z Tradeoffs should be concerned Example 1 z A machine has: z 16 bit instructions z 16 registers (i.e.