Describing and Simulating Dynamic Reconfiguration in SystemC Exemplified by a Dedicated 3D Collision Detection Hardware Dissertation zur Erlangung des Doktorgrades (Dr. rer. nat.) der Mathematisch-Naturwissenschaftlichen Fakult¨at der Rheinischen Friedrich-Wilhelms-Universit¨at Bonn vorgelegt von Diplom Informatiker Andreas Raabe aus Niederkassel Bonn, April 18, 2008 Reviewer: Joachim K. Anlauf, Reinhard Klein Date of oral exam: August 10, 2008 Published: 2008 Diese Dissertation ist auf dem Hochschulschriftenserver der ULB Bonn unter http://hss.ulb.uni-bonn.de/diss_online elektronisch publiziert. This dissertation is publicly available on the server of the ULB Bonn at http://hss.ulb.uni-bonn.de/diss_online in elecronic form. This work was typeset with KOMA-Script and LATEX. For my parents, who provided me such a fine start in life. And for Silke, who loves me how I am. Contents I Introduction 13 1 Motivation 15 2 Project Objectives 19 2.1 Standard Compliance Objective . 19 2.2 IP Objective . 19 2.3 Abstraction Objective . 20 2.4 Integration Objective . 20 2.5 Synthesis Objective . 20 2.6 Connectivity Objective . 21 2.7 Case-Study Objective . 21 3 Choice of Case Study 23 4 Organisation 25 4.1 Document Structure . 25 4.2 Specific Terms Used . 25 II Describing and Simulating Dynamic Reconfiguration in SystemC 27 5 Related Work 29 5.1 Basics . 29 5.1.1 SystemC ................................ 29 A Brief SystemC Methodology Recap . 29 SystemC Simulation Semantics . 32 Elaboration . 32 Simulation . 34 5.1.2 Reconfigurable Platforms . 35 Xilinx Virtex . 36 PACTXPP............................... 37 Conclusion - Architecture Specific Modelling . 37 5.2 High-Level Reconfiguration Modelling . 38 5.2.1 JHDL . 38 Conclusion on JHDL . 39 5.2.2 OSSS+R . 39 5 Contents OSSS .................................. 39 Modelling Reconfiguration with OSSS+R . 41 The OSSS+R Reconfiguration Controller . 44 Conclusion . 44 5.2.3 DRCF . 45 DRCF Approach . 45 Conclusion on DRCF . 47 5.2.4 OCAPI-XL . 49 Reconfigurable Context Switching . 50 Conclusion on OCAPI-XL ...................... 51 5.2.5 Process Control . 51 Concluding Remarks on Process Control Kernels . 52 6 The ReChannel Approach 53 6.1 ReChannel- Basic Features . 53 6.1.1 Modelling Reconfiguration on All Levels of Abstraction . 55 Using Portals To Intercept Communication . 55 Creating Custom Portals . 58 Interface Wrapper . 60 Reconfiguration Callbacks . 61 6.1.2 Rendering Own Components and Third-Party IP Cores Recon- figurable . 62 Creating Reconfigurable Modules . 64 The Module's States . 64 State Preservation . 67 6.1.3 Controlling Reconfiguration Simulation Control . 67 Operating on Sets of Modules . 68 Intermediate Recap . 68 6.2 Advanced ReChannel Features . 71 6.2.1 Reconfigurable Overhead In Static Applications . 71 6.2.2 Accuracy of Reconfiguration Delays . 72 6.2.3 Exportals . 74 6.2.4 Synchronisation Filters . 75 Transaction Counters . 77 Filter Callbacks . 77 Full Implementation of a Synchronisation Filter . 77 6.2.5 Explicit Description of Reconfiguration . 79 Resettable Processes . 80 Resettable Components . 82 6.2.6 Binding Groups of Switches . 83 6.3 ReChannel Simulation Semantics . 84 6.4 Integrating Reconfiguration into the Refinement Process . 87 6.4.1 Functional Level . 87 6 Contents 6.4.2 Transactional Level . 88 6.4.3 Register Transfer Level . 88 III A Dedicated 3D Collision Detection FPGA Architecture 91 7 Related Work 93 7.1 Collision Detection Overview . 93 7.2 Hierarchical Collision Detection . 94 7.3 k-DOPs ..................................... 95 7.4 Separating Axis Test - SAT . 96 7.5 Primitives . 97 7.6 An ASIC Targeted Approach . 97 7.6.1 Bounding Volume Test . 97 7.6.2 Triangle Intersection . 99 7.6.3 The Architecture . 101 DOPArchitecture ........................... 101 Control . 103 Triangle Architecture . 103 Performance Evaluation . 105 7.6.4 Conclusion . 107 7.7 FPGA-Accelerated M¨oller Triangle-Intersection Test . 108 7.7.1 Preprocessing, I/O and Memory Interface . 108 7.7.2 The Architecture . 108 7.7.3 Performance Evaluation . 110 7.7.4 Conclusion . 110 8 CollisionChip: An FPGA-Based 3D Collision Detection Architecture 113 8.1 Space-Efficient Collision Detection . 113 8.1.1 Efficient SAT for k-DOPs ....................... 113 Precomputation . 114 Intersection Testing . 115 8.1.2 Fixed-Point Arithmetic . 116 Correct Fixed-Point Rounding . 116 Bound on Fixed-Point Deviation . 118 8.2 The Architecture . 121 8.2.1 The Pipeline . 121 8.2.2 Overall Design . 123 8.3 Control . 125 8.3.1 Push and Pull Control Architecture . 125 8.3.2 Input FIFO . 127 8.3.3 Optimizing Tree Traversal . 127 8.4 Results of the Basic Architecture . 129 8.4.1 Synthesis Results . 129 7 Contents 8.4.2 Benchmarking . 129 8.5 Defying the Memory Bottleneck . 129 8.5.1 Investigating on Benefits of Caching . 130 8.5.2 Comparing Caching Techniques . 131 LTA Cache . 132 8.5.3 Performance Evaluation and Synthesis Results of the LTA Cache . 134 8.6 Synthesis and Implementation . 134 8.7 The Primitive Test Subsystem . 136 8.7.1 Triangle Intersection Test Review . 136 2 × 2 Linear Equation System, Configuration Space and Determi- nants Approaches . 136 Triangle Transformation . 137 Common Line Intervals . 137 SAT for Triangle Intersection Testing . 138 Choice of Triangle Intersection Test . 139 8.7.2 Integrating the Primitive Test into the Overall Design . 141 Untimed Functional Implementation of SAT for the Primitives . 141 Primitive SAT on RT-Level . 143 The Intersection Test Pipeline . 143 Synthesis Results of the Primitive Intersection Test . 146 IV Putting It All Together 147 9 Applying ReChannel To CollisionChip 149 9.1 Untimed Functional Level . 150 9.1.1 Reconfigurable Topology . 150 9.1.2 Reconfiguration Control . 152 9.1.3 Synchronisation . 152 9.2 Timed Functional Level . 155 9.3 Transaction Level . 155 9.3.1 Communication Latency . 156 9.3.2 Reconfiguration Delay . ..