VLSI UNIT - V Programmable Logic Devices P.VIDYA SAGAR ( ASSOCIATE PROFESSOR) Department of Electronics and Communication Engineering, VBIT CONTENTS SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN: PLAs, FPGAs, CPLDs, Standard Cells, Programmable Array Logic, Design Approach, Parameters influencing low power design. CMOS TESTING: CMOS Testing, Need for testing, Test Principles, Design Strategies for test, Chip level Test Techniques. 2 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Programmable Logic Devices (PLD) General purpose chip for implementing circuits Can be customized using programmable switches Main types of PLDs PLA PAL ROM CPLD FPGA Custom chips: standard cells, sea of gates 3 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P PLDs SPLDs CPLDs PROMs PLAs PALs GALs etc. 4 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P PLD The purpose of a PLD device is to permit elaborate digital logic designs to be implemented by the user in a single device. Can be erased electrically and reprogrammed with a new design, making them very well suited for academic and prototyping Types of Programmable Logic Devices SPLDs (Simple Programmable Logic Devices) ROM (Read-Only Memory) PLA (Programmable Logic Array) PAL (Programmable Array Logic) GAL (Generic Array Logic) CPLD (Complex Programmable Logic Device) FPGA (Field-Programmable Gate Array) 5 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P General structure of PLDs. 6 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P PLD The differences between the first three categories are these: In a ROM, the input connection matrix is hardwired. The user can modify the output connection matrix. In a PAL/GAL the output connection matrix is hardwired. The user can modify the input connection matrix. In a PLA the user can modify both the input connection matrix and the output connection matrix. 7 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Programming by blowing fuses. OR - PLD Notation AND - PLD Notation 8 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P 9 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P ROM Internal Logic Internal Logic of a 32x8 ROM • The decoder stage produces ALL possible minterms • 32 Words of 8 bits each 0 I0 1 • 2 5 input lines (address) I1 3 . • Each OR gate has a 32 input I2 5-to-32 . decoder . • A contact can be made using I3 28 29 fuse/anti-fuse I4 30 31 A7 A6 A5 A4 A3 A2 A1 A0 10 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Programming a ROM Inputs Outputs I4 I3 I2 I1 I0 A7 A6 A5 A4 A3 A2 A1 A0 00000 10110110 x x x xx 00001 00011101 0 I0 1 x x x x 2 x x x x 00010 11000101 I 1 3 x x x x . 00011 10110010 I2 5-to-32 decoder . I3 . 28 x x . I4 29 x x x x 30 x x x . 31 x x x x 11100 00001001 11101 11100010 11110 01001010 A7 A6 A5 A4 A3 A2 A1 A0 11111 00110011 • Every ONE in truth table specifies a closed circuit • Every ZERO in truth table specifies an OPEN circuit • Example: At address 00011 The word 10110010 is stored 11 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Example 1 – Example: Design a combinational circuit using ROM. The circuit accepts a 3-bit number and generates an output binary number equal to the square of the number. – Solution: Derive truth table: Inputs Outputs A2 A1 A0 B5 B4 B3 B2 B1 B0 SQ 000 0000000 001 0000011 010 0001004 011 0010019 100 01000016 101 01100125 110 10010036 111 11000149 12 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Example 1 (cont.) Inputs Outputs A2 A1 A0 B5 B4 B3 B2 B1 B0 SQ B0 000 0000 0 0 0 001 0000 0 1 1 0 B1 010 0001 0 0 4 A0 011 0010 0 1 9 B2 100 0100 0 0 16 B 101 0110 0 1 25 8 X 4 ROM 3 A1 110 1001 0 0 36 B4 111 1100 0 1 49 A2 B5 ROM truth table – specifies the required connections B1 is ALWAYS 0 no need to generate it using the ROM B0 is equal to A0 no need to generate it using the ROM Therefore: The minimum size of ROM needed is 23X4 or 8X4 13 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Example 2 – Problem: Tabulate the truth for an 8 X 4 ROM that implements the following four Boolean functions: – A(X,Y,Z) = Sm(3,6,7); B(X,Y,Z) = Sm(0,1,4,5,6) A X – C(X,Y,Z) = Sm(2,3,4); D(X,Y,Z) = Sm(2,3,4,7) 8 X 4 B Y ROM C Z – Solution: D Inputs Outputs XYZ ABCD 000 0100 001 0100 010 0011 011 1011 100 0111 101 0100 110 1100 111 1001 14 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Sequential Circuit Implementation with ROM inputs X Combinational outputs Z Circuits present state next state FFs • sequential circuit = combinational circuit + memory • Combinational part can be built with a ROM as shown previously • Number of address lines = No. of FF + No. of inputs • Number of outputs = No. of FF + No. of outputs 15 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Example – Example: Design a sequential circuit whose state table is given, using a ROM and a register. – State Table We need a 8x3 ROM (why?) 3 address lines and 3 data lines Exercise: Compare design with ROMs with the traditional design procedure. 16 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Gate Level Version of PLA x1 x2 x3 Programmable connections f = x x +x x '+x 'x 'x OR plane 1 1 2 1 3 1 2 3 P1 f2 = x1x2+x1'x2'x3+x1x3 P2 P3 P4 AND plane f1 f2 17 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P x 1 x2 x3 OR plane f1 = x1x2+x1x3'+x1'x2'x3 P1 f2 = x1x2+x1'x2'x3+x1x3 P2 P3 P4 x marks the connections left in AND plane place after programming f1 f2 18 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Limitations of PLAs PLAs come in various sizes Typical size is 16 inputs, 32 product terms, 8 outputs Each AND gate has large fan-in this limits the number of inputs that can be provided in a PLA 16 inputs 316 = possible input combinations; only 32 permitted (since 32 AND gates) in a typical PLA 32 AND terms permitted large fan-in for OR gates as well This makes PLAs slower and slightly more expensive than some alternatives to be discussed shortly 8 outputs could have shared minterms, but not required 19 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Design for PLA:Example – Implement the following functions using PLA F0 = A + B' C' F1 = A C' + A B Input Side: F2 = B' C' + A B F3 = B' C + A 1 = asserted in term 0 = negated in term - = does not participate Personality Matrix Product Inputs Outputs Output Side: term 0 1 2 3 A B C F F F F 1 = term connected to output A B 1 1 - 0 1 1 0 0 = no connection to output B C - 0 1 0 0 0 1 Reuse A C 1 - 0 0 1 0 0 of terms B C - 0 0 1 0 1 0 A 1 - - 1 0 0 1 20 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Example: Continued A B C AB B’C AC’ B’C’ A Product Inputs Outputs term A B C F F F F 0 1 2 3 F0 F1 F2 F3 A B 1 1 - 0 1 1 0 B C - 0 1 0 0 0 1 Reuse A C 1 - 0 0 1 0 0 of terms B C - 0 0 1 0 1 0 A 1 - - 1 0 0 1 21 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P A A AB AB CD 00 01 11 10 CD 00 01 11 10 A B C D W X Y Z 00 0 0 X 1 00 0 1 X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 01 0 1 X 1 01 0 1 X 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 D D 0 1 0 0 0 1 1 0 11 0 1 X X 11 0 0 X X 0 1 0 1 1 1 1 0 C C 0 1 1 0 1 0 1 0 10 0 1 X X 10 0 0 X X 0 1 1 1 1 0 1 1 1 0 0 0 1 0 0 1 1 0 0 1 1 0 0 0 B B 1 0 1 0 X X X X 1 0 1 1 X X X X K-map for W K-map for X 1 1 0 0 X X X X 1 1 0 1 X X X X A A 1 1 1 0 X X X X AB AB 1 1 1 1 X X X X CD 00 01 11 10 CD 00 01 11 10 00 0 1 X 0 00 0 0 X 1 01 0 1 X 0 01 1 0 X 0 D D 11 1 1 X X 11 0 1 X X C C 10 1 1 X X 10 1 0 X X B B K-map for Y K-map for Z 22 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P 0 0 0 0 0 0 A B C D 23 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P 24 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P 25 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P 26 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Programmable Array Logic (PAL) Also used to implement x 1 x 2 x n circuits in SOP form The connections in the AND plane are Input buffers and fixed connections programmable inverters The connections in x 1 x 1 x n x n the OR plane are NOT programmable P 1 AND plane OR plane P k f1 f m 27 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P x 1 x2 x 3 f1 = x1x2x3'+x1'x2x3 f2 = x1'x2'+x1x2x3 P1 f1 P2 P3 f2 P4 AND plane 28 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P PAL x x x W = ABC + CD X = ABC + ACD + ACD + BCD Y = ACD + ACD + ABD 29 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Comparing PALs and PLAs PALs have the same limitations as PLAs (small number of allowed AND terms) plus they have a fixed OR plane less flexibility than PLAs PALs are simpler to manufacture, cheaper, and faster (better performance) PALs also often have extra circuitry connected to the output of each OR gate The OR gate plus this circuitry is called a macrocell 30 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Macro cell Select Enable OR gate from PAL 0 f 1 1 D Q Flip-flop Clock back to AND plane 31 Department of Electronics and Communication Engineering, VBIT VIDYA SAGAR P Macrocell Functions Enable