Intel® MAX® 10 FPGA Signal Integrity Design Guidelines Subscribe M10-SIDG | 2021.04.27 Send Feedback Latest document on the web: PDF | HTML Contents Contents Intel® MAX® 10 FPGA Signal Integrity Design Guidelines................................................... 3 Definitions.................................................................................................................. 3 Understanding SSN...................................................................................................... 4 Guidelines: Clock and Asynchronous Control Input Signal.................................................. 6 Schmitt-Trigger Input Buffer................................................................................. 7 Guidelines: Data Input Pin.............................................................................................7 Guidelines: Clock and Data Input Signal for Intel MAX 10 E144 Package.............................. 8 Guidelines: I/O Restriction Rules.................................................................................... 9 Guidelines: Placement Restrictions for 1.0 V I/O Pin..........................................................9 Calculating the Total Inductance for 1.0 V Pin Placement........................................ 10 Guidelines: Analog-to-Digital Converter I/O Restriction....................................................12 Guidelines: Voltage-Referenced I/O Standards Restriction................................................15 Guidelines: Adhere to the LVDS I/O Restrictions Rules.....................................................15 Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers..................................... 15 Guidelines: External Memory Interface I/O Restrictions................................................... 16 Guidelines: ADC Ground Plane Connection..................................................................... 17 Guidelines: Board Design for ADC Reference Voltage Pin..................................................17 Guidelines: Board Design for Analog Input.....................................................................17 Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND)........................ 19 Guidelines: Intel MAX 10 Board Design Requirement for DDR2, DDR3, and LPDDR2............ 20 Document Revision History for Intel MAX 10 FPGA Signal Integrity Design Guidelines.......... 21 ® ® Intel MAX 10 FPGA Signal Integrity Design Guidelines Send Feedback 2 M10-SIDG | 2021.04.27 Send Feedback Intel® MAX® 10 FPGA Signal Integrity Design Guidelines Today’s complex FPGA system design is incomplete without addressing the integrity of signals coming in to and out of the FPGA. Simultaneous switching noise (SSN) often leads to the degradation of signal integrity by causing signal distortion, thereby reducing the noise margin of a system. To avoid signal integrity issues, Intel recommends that you follow the design considerations, I/O placement guidelines, and board design guidelines for Intel® MAX® 10 devices regarding: • I/O placement rules • Voltage-referenced I/O standards • High-speed LVDS, phase-locked loops (PLLs), and clocking • External memory interfaces • Analog to digital converter Intel recommends that you perform SSN analysis early in your FPGA design, before the layout of your PCB. Definitions The terminology used in this document includes the following terms: • Aggressor: An output or bidirectional signal that contributes to the noise for a victim I/O pin • PDN: Power distribution network • QH: Quiet high signal level on a pin • QHN: Quiet high noise on a pin, measured in volts • QL: Quiet low signal level on a pin • QLN: Quiet low noise on a pin, measured in volts • SI: Signal integrity (a superset of SSN, covering all noise sources) • SSN: Simultaneous switching noise • SSO: Simultaneous switching output (which are either the output or bidirectional pins) • Victim: An input, output, or bidirectional pin that is analyzed during SSN analysis. During SSN analysis, each pin is analyzed as a victim. If a pin is an output or bidirectional pin, the same pin acts as an aggressor signal for other pins. Intel Corporation. All rights reserved. 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Intel® MAX® 10 FPGA Signal Integrity Design Guidelines M10-SIDG | 2021.04.27 Understanding SSN SSN is defined as a noise voltage induced onto a single victim I/O pin on a device due to the switching behavior of other aggressor I/O pins on the device. SSN can be divided into two types of noise: voltage noise and timing noise. In a sample system with three pins, two of the pins (A and C) are switching, while one pin (B) is quiet. If the pins are driven in isolation, the voltage waveforms at the output of the buffers appear without noise interference, as shown by the solid curves at the left of the figure. However, when pins A and C are switching simultaneously, the noise generated by the switching is injected onto other pins. This noise manifests itself as a voltage noise on pin B and timing noise on pins A and C. Figure 1. System with Three Pins In this figure, the dotted curves show the voltage noise on pin B and timing noise on pins A and C. A B C Voltage noise is measured as the change in voltage of a signal due to SSN. When a signal is QH, it is measured as the change in voltage toward 0 V. When a signal is QL, it is measured as the change in voltage toward VCC. Voltage noise can be caused by SSOs under two worst-case conditions: • The victim pin is high and the aggressor pins (SSOs) are switching from low to high • The victim pin is low and the aggressor pins (SSOs) are switching from high to low Figure 2. Quiet High Output Noise Estimation on Pin B Victim pin B 1 A 0 1 B 0 1 C 0 D E FPGA Package Vias PCB ® ® Intel MAX 10 FPGA Signal Integrity Design Guidelines Send Feedback 4 Intel® MAX® 10 FPGA Signal Integrity Design Guidelines M10-SIDG | 2021.04.27 Figure 3. Quiet Low Input Noise Estimation for Pin D Victim pin B 1 A 0 1 B 0 1 C 0 D E FPGA Package Vias PCB SSN can occur in any system, but the induced noise does not always result in failures. Voltage functional errors are caused by SSN on quiet victim pins only when the voltage values on the quiet pins change by a large voltage that the logic listening to that signal reads a change in the logic value. For QH signals, a voltage functional error occurs when noise events cause the voltage to fall below VIH. Similarly, for QL signals, a voltage functional error occurs when noise events cause the voltage to rise above VIL. Because VIH and VIL of the Intel device are different for different I/O standards, and because signals have different quiet voltage values, the absolute amount of SSN, measured in volts, cannot be used to determine if a voltage failure occurs. Instead, to assess the level of impact by SSN, you can quantify the SSN in terms of the percentage of signal margin in Intel devices. Figure 4. Reporting Noise Margins QHN: 100% QHN: 50% of Signal Margin of Signal Margin Quiet High VIH Min VREF VIL Max Quiet Low QLN: 100% QLN: 50% of Signal Margin of Signal Margin ® ® Send Feedback Intel MAX 10 FPGA Signal Integrity Design Guidelines 5 Intel® MAX® 10 FPGA Signal Integrity Design Guidelines M10-SIDG | 2021.04.27 The figure shows four noise events, two on QH signals and two on QL signals. The two noise events on the right-side of the figure consume 50 percent of the signal margin and do not cause voltage functional errors. However, the two noise events on the left side of the figure consume 100 percent of the signal margin, which can cause a voltage functional error. Noise caused by aggressor signals is synchronously related to the victim pin outside of the sampling window of a receiver. This noise affects the switching time of a victim pin but is not considered an input threshold violation failure. Figure 5. Synchronous Voltage Noise with No Functional Error Asynchronous glitches Synchronous glitches can cause errors are OK VIH VREF VIL Sample Window Guidelines: Clock and Asynchronous Control Input Signal Input clock signal and asynchronous signals are sensitive signals. If signal interference happens at the signal edge, it can cause double sampling issue in internal logic. PLLs are sensitive to SSN jitter generated by nearby I/O pins. Intel recommends that you do not use unterminated I/O standards in the same bank as the input clock signal to the PLL. Intel also recommends instantiating the input clock signal with full rail voltage. Because edge noise is closer to the noise threshold (gap between maximum VIL and minimum VIH), the tolerable noise margin is smaller than the data signal. If the noise falls within the threshold range,